November 04, 2013
This morning Lawrence Livermore National Lab (LLNL) announced a new, purpose-built system designed to tackle specific data-intensive problems using some unique approaches to addressing I/O issues for key "big data" applications in bioinformatics and beyond.
The new Cray CS300 324-node system, dubbed Catalyst, will be bestowed with its inaugural applications sometime in December. Delivered in October, the 150 teraflop cluster sports some notable specs, which LLNL and Intel have commented on in detail below.
One thing that might pop out immediately about these configuration details is that some unique choices have been made in the name of enhancing I/O and overall system balance. The 12-core processor choice, the use of QDR-80, and NVRAM all point to some serious thought about balancing architecture to the requirements of emerging classes of “big data” applications.
As one might imagine scanning the specs list, the spend here is not insignificant, but for a lab that’s focused on HPC, the real thrust of the investment is in the interconnect and I/O tooling versus sheer processing horsepower.
According to Matt Leininger, Deputy of Advanced Technology Projects at Lawrence Livermore National Lab, the combination of non-volatile memory, the latest Intel processors and special focus on the interconnect create the perfect storm for certain data-intensive applications, including those in bioinformatics, as well as for graph analytics and analyzing HPC simulation data.
One of the keys to the system’s data-intensive focus is the choice to use NVRAM in a novel way using some custom-developed technology. LLNL has a number of smaller flash-based clusters that they’ve been tweaking in terms of application middleware or at the OS level so that they can take advantage of NVRAM. During their exploration, they started looking at possible alternatives to the standard MMAP to allow applications to access the NVRAM as if it was actual DRAM memory. The result is their own Data-Intensive MMAP (DIMMAP) which handles the intelligence of the caching process and outshines Linux MMAP.
Leininger pointed to a bioinformatics application that had scaling problems. It now uses their DIMMAP technology on the backend to load large databases into NVRAM, enabling a new set of analytical options that weren’t possible before (or required reads and writes from disk, which killed performance). They have already been able to demo the success of DIMMAP on a smaller research cluster and the team is looking forward to taking advantage of Catalayst.
Mark Seager, CTO of Technical Computing at Intel, these choices push the relatively small Catalyst into 60 million IOPS territory. As he explained, “These devices are in the range of 150-200k IOPS per device and Catalyst has one on every node, so there’s 300 of them on compute nodes—and three on the buffer nodes. The bandwidth in aggregate out of these flash devices is comparable to what’s on the Sequoia system. They have a half terabyte per second of IO bandwidth out of Sequoia to a Luster parallel file system and we’ll have a half terabyte per second at these IOPS rates to these local flash drives on catalyst at a fraction of the cost. That’s a game changer.”
The other "game changer" for Livermore is hopping the single-rail barrier. As Leiniger noted, LLNL has been a TrueScale QDR shop for several years, but this system marks a new phase in that usage with their shift into dual-rail. With a typical cluster, if there’s one HCA it’s directly connected to one socket and while network performance off that one is great, when you communicate to the other, the extra hops sling a performance hit. As Leininger said, “dual rail offers more balanced performance and we expect that the dual rail QDR will be as good or better than any other technology on the market.”
According to Seager, “Even though EDR is faster in terms of the transmission rate per channel, the fact that we have two QDR channels in aggregate means there’s a lot more bandwidth coming off the node than with EDR. Since the TrueScale fabric does most the processing in software o the cores, as you go with a highly parallel processor, it’s possible to scale much better with one MPI task per core.”
Seager continued pointing out that even though while not all the bandwidth is available per channel, this is not really the issue because it’s not really used that way. “You never use it with one MPI task or one processor trying to use the whole channel. Typically, all of the MPI tasks on the node are all trying to use the interface and it’s really that aggregate throughput.”
Leininger said that this is an ideal configuration as they have several PCIe flash cards on the gateway nodes, which are separated and attached to PCIe directly. This means it’s possible to directly from the adapter to the processor without having to transfer across QPI. “It’s well balanced in terms of bandwidth of PCIe flash and the QDR interconnect,” he concluded.
One of the reasons why Intel is interested in this configuration is that they’re looking at how the usage of the system will evolve around LLNL’s emerging data intensive computing model. As Seager said, “there are specific apps that have been targeted but we’re also looking at how, once people start looking at this architecture differently, they’ll come up with new use models to help us learn what the next generation of applications will look like.”
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