October 23, 2013
This week Intel announced a new initiative, called the Intel Parallel Computing Center program, which is designed to help users across the wide sphere of technical computing as they modernize their applications to take advantage of the new levels of parallelism that are present now—and will be ubiquitous in the systems of the future.
According to Raj Hazra, VP of Intel's Architecture Group, “As we look to reaching exascale high performance computing by the end of the decade, we have to ensure that the hardware doesn’t get there and leave the applications behind. This means not only taking today’s applications and optimizing them on parallel architectures…but also co-designing future application software and the future versions of these architectures to achieve optimal performance at all levels—from the computing node to the entire system.”
James Reinders, director of business development and marketing for Intel's Software Products Division, says, “Parallel computing challenges are about enabling the future of computing, not just tuning for one hardware direction or another.” He says that his belief in the new program is fed by the questions and complaints he regularly fields from users, including that their algorithms can’t run in parallel, can’t scale beyond 20 cores or that they can’t make their code vectorize. Reinders says he hopes the “results will help break new ground, which will provide valuable lessons for us all, while yielding practical benefits in important open source applications.”
Joe Curley, Director of Marketing in Intel's Technical Computing Group, told us that the teams at Intel have already gone through a number of enablement cycles for other parallelization projects, including the lead up to releasing the Xeon Phi coprocessor. During that process, they discovered a lot about Xeons and the lack of ability of many applications to harness the capability of sheer parallelization. However, by modernizing applications and in many cases, restructuring the kernel of specifics applications to be able to take advantage of modern clusters (and those coming in the future) we will see an era of many applications that can grow with the performance increases offered by new hardware.
There are many codes that are still widely used but were built for machines from 30 years ago and don’t map well to the highly parallel machines of today, said Curley. He points to a number of examples, including award-winning research that showed how the parallelization of a life sciences application led to a 20x performance increase but with application modernization by kernel restructuring, the resulting performance showed a 2000x boost.
Curley says that Intel’s research partners want to continue to work to modernize codes to meet the needs of upcoming systems as they have in the past via Intel Labs, but they’ll now be bringing their research and code modernization to a wider array of technical computing users. The difference between this and Intel Labs research is that Intel usually hasn’t focused its research partnerships on delivering community codes and community-driven products. However, this open call for application modernization, which will be handled via a web portal and the ability to submit a proposal (in much the same one might request grants) will usher in a new era of modern applications primed to handle the new age of hardware that Intel and others are pushing.
Raj Hazra detailed some of the work being done with the pilot project members of their Intel Parallel Computing of the program, including CINECA, Purdue University, TACC, The University of Tennessee, and Zuse Institut Berlin (ZIB). They are described in more detail below:
CINECA - Parallelization of codes like Quantum Espresso an integrated Open-Source suite of computer codes for electronic-structure calculations and nanoscale materials modeling are the target.
Purdue - optimizing the performance of the NEMO scientific simulation suite of software tools (which is code that Intel uses, by the way).
The University of Tennessee - Gromacs and PHOENIX a program to model the atmospheres and synthesize the spectroscopic features of astronomical objects Blast. Additionally they have a project is developing MAGMA MIC, a new generation of highly optimized linear algebra libraries for the Intel MIC architecture.
TACC - Memory Access Centric Performance Optimization tool, or MACPO, generates memory traces of the important data structures by code segment. These memory traces are processed to determine the access and reuse patterns of data in each thread for each structure, allowing new levels of parallel code optimization. Over time we expect this tool to have broad impact.
ZIB’s Research Center for Many-core High-Performance Computing will foster the uptake of current and next generation Intel many- and multicore technology in high performance computing and big data analytics. They are focusing on a diverse set of codes including VASP which is targeted at atomic scale materials modeling.
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