October 16, 2013
Analyst firm Communications Industry Researchers (CIR) has released a new report covering the latest developments in optical interconnection at the chip level and the progress in this area that is being made by research teams throughout the world.
With the current era of multicore processors and 3D chips, computing speeds are limited by how fast CPUs can communicate with each other and with memory devices. "So reliable, low-loss, high-speed interconnects between chips then becomes crucial," notes CIR. "Interconnect data rate requirements could reach hundreds of times what they currently are today."
According to the Charlottesville, Virginia-based industry analyst firm, "the addressable market for chip-level optical interconnects could eventually run into billions of units and revenues in this market will total almost $520 million by 2019 going on to reach $1.02 billion by 2021."
A new report titled "Revenue Opportunities for Optical Interconnects: Market and Technology Forecast – 2013 to 2020 Volume II: On-Chip and Chip-to-Chip" continues the firm's analysis of this market dating back to 2009. The latest findings are a follow-up to an August 2013 report, titled, "Revenue Opportunities for Optical Interconnects: Market and Technology Forecast – 2013-2020. Vol. I Board-to-Board and Rack-Based."
"Volume II: On-Chip and Chip-to-Chip" highlights four kinds of chip-level interconnect: optical engines, photonic integrated circuit (PIC)-based interconnects, silicon photonics and free-space optics. The report includes nine-year forecasts as well as an overview of the latest business and technology strategies in the chip-level optical interconnect space. Among the vendors and manufacturers mentioned in the report are Avago, Cisco, Corning, Dow Chemical, Dow-Corning, DuPont, Finisar, Fujitsu, Furukawa, IBM, Intel, Juniper, Kotura, Micron, Novellus, Optical Interlinks, QD Laser, Reflex Photonics, Samtec, Sumitomo, TeraXion, Tokyo Electron, ULM Photonics, and VI Systems.
"The growing popularity of parallel computing, and the arrival of multicore processors and 3D chips are leading to data traffic jams both on-chip and chip-to-chip," observes CIR. "However, ... these trends are also creating opportunities for chip-level optical interconnects."
Avago, Finisar, IBM and Samtec have all proposed optical engines for chip-level interconnect, which could lead to revenues of $235 million by 2019, according to CIR. Currently, these miniaturized optical assemblies represent the most mature technology for this application. Once connectors and heat sinks are factored in, however, such optical engines may prove too large for complex optical interconnection environments, like those required by exascale supercomputers.
Given the current limitations of optical engines, there is an opportunity for compact PIC-based interconnect devices based on indium phosphide and gallium arsenide. CIR says these technologies will generate $120 million in 2019 increasing to $275 million by 2021. Because bonding PIC interconnects onto a silicon processor or memory chip is a difficult and expensive endeavor, only a few PIC and VCSEL technology companies are developing this technology.
CIR also discusses the current state of silicon photonics, which despite promising tantalizing benefits remain always just out of reach for firms like Intel which have struggled for years to develop active optical devices based on silicon. "A breakthrough in silicon laser technology would be the single most important development in optical interconnects allowing the full integration of both electronic information processing and optical integration," writes the analyst house.
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?