May 20, 2013
May 20 -- Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market.
“Tezzaron specializes in 3D wafer stacking and TSV processes. We work with dozens of customers to create custom 3D-ICs for prototyping and commercialization, including recent 3D-ICs in 40 nm and 65 nm, the first at these small nodes.”
“Tezzaron specializes in 3D wafer stacking and TSV processes. We work with dozens of customers to create custom 3D-ICs for prototyping and commercialization, including recent 3D-ICs in 40 nm and 65 nm, the first at these small nodes,” said Robert Patti, CTO and VP of design engineering at Tezzaron Semiconductor. “By collaborating with Mentor Graphics, we can offer our mutual customers a comprehensive design verification solution. It creates the highest value for them with the least disruption to their existing flows. Using Calibre, our customers get the best possible turnaround time. Even better, there is no need to generate a ‘Frankenstein’ GDS file combining all the individual dies in a 3D-IC assembly, and no need to deal with a ‘monster’ rule file combining different die processes. Calibre makes the process very fast and relatively easy.”
Tezzaron works with industry, academia, and government to create advanced 3D-ICs. Their offerings include wafer stacking and die stacking technology with TSVs, Bi-STAR built in self-test and repair circuitry for continuous error detection and recovery, and extremely fast memory devices for both standalone and stacked applications.
Complementing Tezzaron’s 3D-IC design capabilities, the Calibre 3DSTACK signoff solution provides DRC, LVS, and parasitic extraction (PEX) capabilities. It verifies physical offset, rotation, and scaling at the die interfaces. It also enables connectivity tracing and extraction of interface parasitic elements needed for multi-die performance simulation. The Calibre 3DSTACK product is a fully compatible extension to the standard Calibre signoff platform, so it can be easily added to existing verification flows to support flexible stacking configurations of multiple dies, including dies based on different technologies or process nodes.
“Over the last two years, the relationship between Mentor Graphics and Tezzaron has really blossomed as we work together to bring volume 3D-IC applications to the IC industry mainstream,” said Michael Buehler-Garcia, senior director of marketing for Calibre Design Solutions at Mentor Graphics. “Combining flexibility, ease-of-use, and interoperability provides the highest value for our mutual customers, and will help make the adoption of 3D-IC design techniques successful.”
Tezzaron Semiconductor Corporation is a world leader in the design and production of 3D-ICs built with through-silicon vias (TSVs). Tezzaron also builds patented ultra-high-speed memory products. Tezzaron’s products and technologies have applications in defense, super-computing, high speed telecommunications, and anywhere that speed, reliability, and power optimization are needed. Corporate headquarters are located at 1415 Bond Street, Suite 111, Naperville, Illinois 60563. World Wide Web site: http://www.tezzaron.com/.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of about $1,090 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Source: Mentor Graphics
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?