March 29, 2013
It appears that Intel is looking for a program lead to back its exascale initiatives. The chip giant has put out feelers for a Senior Exascale Program Architect, who will be the “key person driving and growing the path-finding portfolio of the Exascale System Path-Finding group.”
The company notes that the right person will have a broad contact network within and outside of Intel. Intel notes that the role would involve shaping the existing portfolio of exascale initiatives and extensive “deep interaction with a variety of external expert customers in the DoE, DoD, NSF and other federal agencies” as well as with members of Intel Research.
The DoE has already doled out contracts to Intel and other chip vendors, including AMD and Intel to explore new technologies that can lead us into an efficient exascale era via the FastForward effort. Intel’s Federal initiative received close to two million to focus on processor efficiency and next-gen memory technologies (as was AMD, but with less than $10 million). NVIDIA also received just a tick over $12 million to address the same issues, but also to work on signal technologies and new programming approaches that can work toward “efficient exascale.”
The exascale “pathfinding” group doesn’t seem to have much of a public presence as nothing shows up about it, but it is clear that Intel is building its plans to be at the fore of eventual exascale systems. One can safely speculate that the recent release of Phi and building exascale ambitions have necessitated a new internal division.
As the job description for this Oregon-based position notes, the Senior Exascale Program Architect should fit the following bill:
-Extensive knowledge of and experience with the entire palette of multi-disciplinary technologies that influence future HPC architectures - hardware, software, applications and systems.
-Ability to quickly learn and ramp up on new technologies.
-Ph.D. in Engineering, Computer or Computational Science, or related field.
-Wide contact network, internal and external to Intel.
-Deep understanding of the federal funding program culture.
-Visionary, innovative, out of the box thinker.
-At least 15 years of relevant experience in both programmatic and technical roles - recognized stature in the community.
-Ability to define and articulate a wide holistic system view, while also being able to dive deep into complex technical considerations.
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?