July 05, 2012
There has been a lot of discussion regarding the end of Moore’s Law, almost since its inception. Renowned leaders in high performance computing and physics have predicted scenarios detailing how chip advancements will eventually come to a halt. Last week, IEEE Spectrum dedicated a podcast to the subject and talked about a number of design changes aimed at extending silicon’s viability.
In a recent IEEE Spectrum article, associate editor Rachel Courtland explained that silicon has become increasingly difficult to work with as semiconductor manufacturers continue to push the physical limits of the technology. Transistors have become so small, that they have begun to leak electrical current. This problem has led to a search for new technologies that may eventually replace or enhance conventional chip designs.
Courtland met up with Bernd Hoefflinger, editor of Chips 2020, a book written by experts in the field explaining their thoughts regarding the future of computing. In Courtland’s interview, Hoefflinger noted that computational performance is not the only issue at hand. The power consumed by these technologies has a profound impact on their practicality. Said Hoefflinger:
“They expect 1000 times more computations per second within a decade. If we were to try to accomplish this with today’s technology, we would eat up the world’s total electric power within five years. Total electric power!”
He was referring to Dennard’s scaling, which is related to Moore’s Law. Essentially, as transistors get smaller, they will increase in speed and consume less power. Unfortunately, this phenomenon is losing steam and overcoming this limitation has become a primary focus by semiconductor designers. Hoefflinger believes if the power needed to compute a simple multiplier could be reduced to 1 femtojoule, silicon will keep Moore’s Law alive for the next decade. A femtojoule is roughly 10 percent of the energy fired from a human synapse.
To reach these low-power benchmarks, new 3-D circuit designs have emerged. Currently, 3-D chips have entered the market, using wires to connect multiple dies together. In addition, tri-gate or FinFET transistors have been developed, but Hoefflinger thinks that another design holds more promise.
According to him, 3-D merged transistors can be developed that combine two transistors into a single device. Instead of designing p-doped and n-doped transistors with their own gates, they share a gate with a PMOS transistor on one side and a NMOS transistor on the other side. These have sometimes been referred to as “hamburger transistors.”
Another method to reduce power has to do with how calculations are performed. For example, if multiplication was performed starting with the most significant bits (rather than the least significant bits), it could reduce the amount of transistors required for a calculation. While the reduction might not drop the energy to one femtojoule, it may bring consumption down “by an order of magnitude or two”.
Lastly, Hoefflinger suggested changing chip circuit architecture similar to communication circuitry. The change in design would allow for an integrated error correction, also leading to lower operational voltage.
If all of these suggestions for power reduction are implemented, it may extend Moore’s Law beyond 2020. Hoefflinger believes it could go either way, but is encouraged by the fact that these issues are getting a lot of attention right now.
Full story at IEEE Spectrum
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