June 18, 2012
Intel's first Many Integrated Core (MIC) microprocessor is now just months away from its commercial debut. On Monday at the International Supercomputing Conference (ISC'12) in Hamburg, Intel announced that Knights Corner, the company's first manycore product, would be in production before the end of 2012. The company also released a few more details about the upcoming product line, including the creation of a new Xeon brand for the architecture, some performance updates on pre-production silicon, and Cray's adoption of MIC as part of its future Cascade supercomputer.
This was not a Knights Corner launch, however. With the plans now set for the chip to go into production before the end of the year, more than likely that means Intel will debut the product, in all its manycore glory, at SC12 in November. NVIDIA's big Kepler GPU, the K20, is also expected to launch around this time, setting the stage for an MIC-GPU shootout in Q4.
This fall, TACC is slated to get a boatload of the first MIC coprocessors -- 8 petaflops worth -- as part of the center's 10-petaflop Stampede supercomputer, which will be built by Dell. Other Knights Corner systems are also in the works for a handful of large HPC centers, including Jülich Supercomputing Centre, the University of Tokyo, Leibniz Supercomputing Centre (LRZ), Oak Ridge National Laboratory, the Korea Institute of Science and Technology Information (KISTI) and CERN. Depending upon the actual installation schedules and availability of the MIC parts, some or all of these systems may be up and running by November, in time perhaps to log Linpack runs.
But we won't have to wait for November to hear about Linpack running on MIC machines. According to Intel's Rajeeb Hazra, Intel's GM of the Technical Computing group, they've been running the High Performance Linpack (HPL) benchmark on pre-production parts and have been able to achieve one teraflop on a single node equipped with a Knights Corner chip. That teraflop, by the way, is provided by the Knights Corner card plus the two Xeon E5 host CPUs, so the MIC chip itself is likely delivering something in the neighborhood of 700 to 800 gigaflops.
Intel has also put together a Xeon E5-MIC experimental cluster with pre-production Knights Corner parts that delivers 118.60 Linpack teraflops. That's enough to place it at number 150 on the new TOP500 list released earlier today.
The peak performance for the Intel MIC cluster is 180.99, which means the Linpack yield is only 65 percent. Even though that's pretty anemic compared to a CPU-only cluster, which typically hit 75 to 95 percent of peak, compared to the 50 percent or so yield on the current crop of GPU-accelerated clusters, MIC's Linpack extraction looks to be significantly better. NVIDIA's latest Kepler GPU and GPUDirect technology may help to close that gap, but we'll have to wait and see on that.
Since Intel is not doing the Knights Corner launch at this point, they're not releasing much more information about the upcoming product here at ISC. All the previous specs -- 50-plus cores on 22nm process technology -- are still in effect.
Intel, however, did talk about the on-board memory for the first time, saying that the Knights Corner PCIe cards will include at least 8 GB of GDDR5 memory (which, by the way, may have contributed to the better Linpack yield). The current Fermi-based Tesla modules from NVIDIA top out at 6GB of GDDR5, but the upcoming K20 module is likely to get more than that. Intel is still mum about ECC support for Knights Corner's on-board memory, but as we've said before, such support seems like a foregone conclusion.
On the marketing front, the product line is getting a rebrand makeover. The architecture will still be called MIC, but the official product family will now be known as Xeon Phi. The idea here was to leverage the well-established Xeon brand, which defines the leading edge of Intel's x86 line-up. At the same time, it drives home the point that MIC is an x86-based architecture, rather than some exotic design that Intel cooked up only for bleeding-edge techies.
Although the MIC instruction set, which Intel made public last week, does not match that of the latest Xeon CPUs, bit for bit (mainly diverging in the vector instruction area), the company is quick to point out that its C and Fortran compilers, libraries and other development tools will support the new architecture seamlessly. Plus, we're reminded, developers are free to program them with the HPC standard parallel frameworks, namely MPI and OpenMP, as well as Intel's own frameworks like TBB and Cilk Plus. Basically, if an app runs on a Xeon, it should run on a Xeon Phi.
In fact, Hazra made a point of talking up the ability of the Phi chips to run entire applications, rather than just accelerated kernels as is the case for GPUs and FPGAs. According to him, you will be able to run complete apps on the coprocessors, which can be treated as a virtual network node. That belies MIC's natural role as a coprocessor, but opens up some unique ways to use the chip, as well as helping ease application porting and development.
Intel has to a careful here. Many, if not most, HPC applications are likely to run slower if they are entirely confined to a MIC coprocessor, in part because single-threaded performance on MIC will be inferior to that of a Xeon CPU. Plus, even at 8 GB, local memory capacity on the Phi card is just a fraction what a CPU can access.
And Intel still promotes its beloved Xeon CPUs as the center of the high performance computing universe, with Hazra referring to them as "the foundation of HPC" for general-purpose technical computing workloads. The Xeon Phi chips, he says, are suited for those applications that are highly parallel in nature. But the latter and former have a huge overlap, so talk of using the coprocessor as a CPU seems to send somewhat of a mixed message to HPC'ers.
In any case, OEMs are jumping on the MIC bandwagon. Most of the HPC system vendors in the x86 clusters business today will be offering Xeon Phi-equipped systems, presumably as soon as the first Knights Corner chips start rolling out, or soon thereafter. All the major server makers have signed up, including IBM, HP, Dell, Bull, SGI, and Fujitsu, as well as smaller HPC outfits like Appro, T-Platforms, and Penguin Computing.
Cray too, will be introducing MIC supercomputing in their "Cascade" product line in 2013, a system that will glue Xeon CPUs to Phi coprocessors. Cascade is the result of the DARPA HPCS program, whose goal was to produce productive architectures for multi-petaflop computing. The addition of the MIC chips to Cascade should come as no surprise, given that the system was designed to be based on Intel parts from the get-go.
"This is the next big step in our adaptive supercomputing vision," said Cray CEO Peter Ungaro. According to him, they've already begun taking orders for such Phi-accelerated systems, including one from HLRS at the University of Stuttgart in Germany and another from Kyoto University in Japan.
Although the Xeon Phi product will be initially aimed at traditional HPC science codes, Intel believes that other applications that require high levels of parallelism, especially data parallelism, would also be good candidates. Big data analytics, in particular, appears to be an area ripe for these manycore processors with lots of memory bandwidth, and both the Xeon Phi and NVIDIA GPUs are likely to be jockeying for a chunk of this market.
The idea of using the MIC platform as the basis for big data machines has piqued Cray's interest too. "We actually see Phi as a very viable candidate even within that [big data] environment," said Ungaro. uRiKA, Cray's big data appliance, which it offers under its YarcData division, is currently based on the company's own custom Threadstorm processor.
Being able to sell these manycore chips into multiple markets beyond HPC would certainly be appealing to Intel and is likely to affect the Xeon Phi roadmap going forward. In the meantime, users will have to wait for Knights Corner launch, which finally appears to be just around the corner.
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