November 29, 2011
16GT/s increases I/O bandwidth, scaling the interconnect to meet emerging application requirements
BEAVERTON, Ore., Nov. 29 -- PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) industry-standard input/output (I/O) technology, today announced the approval of 16 gigatransfers per second (GT/s) as the bit rate for the next generation of PCIe architecture, PCIe 4.0. This decision comes after the PCI-SIG completed a feasibility study on scaling the PCIe interconnect bandwidth to meet the demands of a variety of computing markets.
After technical analysis, the PCI-SIG has determined that 16GT/s on copper, which will double the bandwidth over the PCIe 3.0 specification, is technically feasible at approximately PCIe 3.0 power levels. The data also confirms that a 16GT/s interconnect can be manufactured in mainstream silicon process technology and can be deployed with existing low-cost materials and infrastructure, while maintaining compatibility with previous generations of PCIe architecture. In addition, the PCI-SIG will investigate advancements in active and idle power optimizations, key issues facing the industry.
"The PCI Express architecture has become the de facto I/O technology within the industry, in large part due to PCI-SIG's dedication to I/O innovation and the insight of those who defined earlier versions in such an extensible manner," said Nathan Brookwood, research fellow at Insight 64. "Like its predecessors, the PCIe 4.0 architecture is well positioned to preserve the industry's investments in earlier generations of PCI Express specifications while extending the technology in a manner that enables new applications and usage models."
Approximately 24 billion lanes of PCIe have shipped in the marketplace since its introduction--a strong testament to the industry's reliance on PCIe architecture as an open bus standard now and for the future. This next-generation PCIe architecture, while doubling the data rate, will maintain its position as a low-cost, high-performance I/O technology. PCIe 4.0 technology will maintain backward compatibility with previous PCIe architectures and provide the optimum design point for high-volume platform I/O implementations across a wide range of existing and emerging applications. The PCIe 4.0 specification will address the many applications pushing for increased bandwidth at a low cost including server, workstation, desktop PC, notebook PC, tablets, embedded systems, peripheral devices, high-performance computing markets and more.
"Experts in the PCIe Electrical Workgroup carefully analyzed a number of target bit rates for the next generation of PCIe architecture, taking into consideration several key factors, including our ability to continue using low-cost materials. We have concluded that 16GT/s is a feasible technical solution that satisfies our member companies' requirements," said Al Yanes, PCI-SIG chairman. "While the preliminary analysis is encouraging, a lot more challenging work lies ahead in developing the specifications. The PCI-SIG looks forward to providing our members with a specification that not only satisfies their high performance requirements but also meets their power, cost and compatibility goals."
The final PCIe 4.0 specifications, including form factor specification updates, are expected to be available sometime in the 2014-2015 timeframe.
PCI-SIG members can participate in the review of all PCI specifications before they are released to the industry. PCI-SIG members develop and maintain PCIe specifications, including the PCIe 4.0 specification, and are actively involved in defining compliance criteria and other technical enabling collateral.
As an additional and extremely valuable benefit of PCI-SIG membership, members are given the right to receive patent licenses from any other member of the organization with necessary claims of patent embodied within the specifications. These licenses may be limited in scope to an implementation of a particular specification, but must be granted to all members on reasonable and non-discriminatory terms. To join the PCI-SIG, visit www.pcisig.com/membership .
PCI-SIG is the consortium that owns and manages PCI specifications as open industry standards. The organization defines industry standard I/O (Input/Output) specifications consistent with the needs of its members. Currently, there are more than 10,000 individuals participating from the PCI-SIG's more than 800 industry-leading member companies. For more information and a list of the board of directors, visit www.pcisig.com .
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?