October 24, 2011
According to an EE Times article published last Friday, Intel is getting set to launch its Ivy Bridge CPUs in March 2012. That is about 3 months later than the original schedule, which had the first chips slated for a debut in late 2011. The updated schedule was revealed by Intel CEO Paul Otellini, during an earnings call conducted last week.
Nevertheless, Tom's Hardware Guide pointed out the Ivy Bridge parts are on target for a "qualification for sale" in late 2011. That would allow Intel to maintain that they fulfilled their 12-month tick-tock cadence, even though shipping CPUs would not appear until the spring.
The Ivy Bridge delay is related to moving Intel's manufacturing technology from 32nn to the new 22nm process, according to the EE Times piece. The new technology is not just a simple shrink, but involves transitioning from Intel's current planar design to its 3D Tri-Gate transistor technology that the chipmaker unveiled in May. Intel has been touting the Ivy Bridge CPUs as the first high-volume chips to employ 3D transistors.
According to the Intel, the Tri-Gate technology will enable a 50 percent power reduction at constant performance or a 37 percent performance increase at low voltages when compared to the 32nm technology that they're currently shipping with the Sandy Bridge parts.
The Ivy Bridge CPUs that will appear in March will be for desktops and other client-side platforms, with the server versions coming later, although apparently Otellini didn't commit to any dates on those. The 32nm Sandy Bridge Xeon-EP server (Xeon E5) CPUs are on track to be released in Q4 2011 (2-socket) and Q1 2012 (4-socket). The E5 server chips are also a quarter behind their original launch, but since AMD's new Interlagos CPUs lagged as well, Intel was able to slip its Xeon rollout without losing any ground.
Even with the later-than-planned rollout of Ivy Bridge, Intel will still be the only chipmaker producing volume processors on 22nm technology.
Full story at EE Times
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?