October 03, 2011
In May, chip startup Adapteva debuted Epiphany, a manycore architecture designed to maximize floating point horsepower with the lowest possible energy footprint. The initial silicon was a 16-core processor, implemented on the 65nm process node. This week, the company announced it has taped out a 64-core version of the design on the 28nm process node, delivering 100 gigaflops of performance at under 2 watts of power.
The three-year old company is targeting the two extremes of the computing spectrum with their Epiphany architecture: supercomputing and mobile devices. The common denomination in both cases is an obsession to minimize power consumption, something the Adapteva designers have done extremely well.
According to Adapteva founder and CEO Andreas Olofsson, this latest silicon, officially known as Epiphany-IV (it's the fourth generation of the architecture) runs at 800 MHz and is expected to achieve 70 single precision gigaflops/watt, twice the efficiency of their previous design. Their fab partner, GLOBALFOUNDRIES, is expected to start churning out samples of the 64-core wonder in January 2012.
As we reported in May, the RISC-based Epiphany design employs a 2D, low overhead, low latency mesh for inter-core communication, with each core containing 32KB of local memory for explicit cache control (in order to maximize data movement efficiency). Although the latest design implements 64 cores, Adapteva is projecting processors with as many as 4,096 cores per chip, delivering upwards of 4 teraflops.
While the company can't claim a design win in either the HPC or mobile world, embedded device maker BittWare has picked up the Adapteva chip for one of its FPGA Mezzanine Cards (FMCs). That product pairs four Epiphany 16-core processors with an Altera Stratix FPGA. The sub-10 watt card delivers 128 gigaflops and is aimed at applications such as digital signal processing, defense, and communications. Although Olofsson is thrilled to get BittWare's business, he thinks their are much larger opportunities to be had if he can find some other enterprising partners.
For example, he believes the new 64-core version, officially known as would be ideal for a tablet PC, smartphone, or an HPC board. In the latter case, Olofsson envisions an array of Epiphany chips on a board that can be plugged into an HPC server node (or a whole cluster), to offload floating-point intensive workloads. The chip array would be hooked together as an extension of the on-chip communication fabric that connects the individual cores. "You could easily fit a couple of teraflops on a board at a very reasonable power consumption," Olofsson told HPCwire.
The CEO says his five-man company is profitable now, but they need a deep-pocketed partner or two to take to technology to the next level. In particular, Epiphany would benefit greatly from a more complete software stack -- compilers, debuggers, libraries and so on -- to attract developers. The current Epiphany SDK, which provides an ANSI C development environment, is fine for the development kits Adapteva is handing out, but they'll eventually need a production toolset if they hope to become a major manycore vendor.
The competition is already rather formidable. Intel, with its Many Integrated Core (MIC) x86 processor for high performance computing, has vast resources to develop and support that architecture. MIC will inherit Intel's parallel software portfolio, making it automatically attractive to an established audience of developers. Although not set to debut until late 2012 or early 2013, Intel's manycore offering already has a chalked up a major win in TACC's "Stampede" supercomputer.
The other established manycore vendor, Tilera, already has 64-core chips in the field. In this case though, the architecture is more oriented toward general-purpose processing, rather than a floating point acceleration, so is mainly being targeted to cloud computing, networking, and multimedia applications.
Although the new breed of GPGPUs from NVIDIA and AMD are also being used as floating point accelerators, Olofsson doesn't equate those designs with Epiphany, which relies on a more conventional CPU-type of architecture. And while he thinks both CUDA and OpenCL are worthwhile execution models for parallel programming, Olofsson believes the data-parallel-centric GPU design has too many restrictions. "GPUs are the answer for graphics," he says. "I dont think they are the answer for HPC."
Adapteva, with its laser focus on floating point performance and with no allegiance to either the x86 instruction set or graphics support, is able to squeeze a lot more performance per watt out its design. For example, the 32-core MIC prototype, Knights Ferry, delivers 1200 gigaflops of peak single precision performance. Assuming a power draw of 200 watts (which is probably on the conservative side), that translates to a performance efficiency of 6 SP gigaflops/watt.
That's a far cry from the 35 SP gigaflops/watt Adapteva has already demonstrated, and even if Intel doubles or quadruples its efficiency when it launches the production Knights Corner MIC, by that time Adapteva should already have its 70 gigaflops/watt chips in the field. Even the upcoming Kepler GPU from NVIDIA is expected to deliver only about 10 SP gigaflops/watt.
If Adapteva's story of a proprietary floating point accelerator sounds like a remake of the ClearSpeed story, that's not quite the case. Olofsson maintains they are only in the semiconductor design business, with has no aspirations to churn out production processors, boards, and systems, like ClearSpeed tried to do. According to him, the idea is to entice other chip and board makers to license the technology, the same way ARM Holdings does for its microprocessor IP.
Speaking of which: ARM processor and device vendors could be ideal companions for Adapteva, given ARM's penetration into the mobile space. In fact, Olofsson admits there is a tier 1 semiconductor vendor who is evaluating the Epiphany technology right now, and it's a fair bet that the company is already an ARM licensee. The idea would be to either integrated the Epiphany design on-chip next to ARM cores, or just pair Epiphany chips with ARM processors on a card.
Perhaps a more interesting scenario is for AMD to license Epiphany (or even acquire the company outright). Even though AMD is using its GPGPU technology to target HPC and their mobile ambitions, Epiphany would give them a cutting-edge accelerator technology to go head-to-head with Intel's MIC architecture. It would also enable AMD to develop some rather unique mobile processor silicon to pair with their low-power x86 CPU designs.
In the short-term, one of Olofsson's dreams is to get someone to build an Epiphany-equipped computer that can run Linpack (presumably, with a double precision floating point implementation of Epiphany) to get a Green500 ranking. The current champ is an IBM Blue Gene/Q prototype machine, which is based on a PowerPC A2 SoC that delivers about 3.7 gigaflops/watt (which, by the way is about what ClearSpeed's ASIC was delivering in 2008 before the company unraveled). With its 10-fold performance per watt advantage, Olofsson thinks an Epiphany-based system could easily capture the number one spot on the Green500 list.
Although Adapteva has taken a somewhat unconventional approach with its manycore chips, Olofsson says their design will scale much better than legacy CPU architectures, like the x86, and will be much more efficient at extracting floating point performance than generalized graphics processors. And even though he's battling much larger and wealthier semiconductor vendors, Olofsson likes his chances. "Multicore and manycore is the future of computing," he says, "and we feel like we're right in the middle of it."
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?