September 22, 2011
The HPC contingent at NVIDIA must be stinging a bit today when they learned of Intel's first big Many Integrated Core (MIC) win at the Texas Advanced Computing Center (TACC). The 10-petaflop super, named Stampede, is scheduled to boot up at the end of 2012, and will have 8 petaflops worth of Intel's manycore Knights Corner coprocessors.
The NSF, who funded the system, is shelling out $2.5 million for thousands of MIC chips -- money that would probably be going to NVIDIA's bottom line had Intel stayed out of the HPC coprocessor biz. More disturbing for NVIDIA perhaps is that Intel doesn't even have production parts in the field, but managed to convince the NSF, TACC and its partners that MIC was the way to go. When I spoke with TACC Director Jay Boisseau, he told me that the manycore chips they expect to be getting in the fall of 2012 are pre-production Knights Corner parts, but otherwise identical to the final version.
TACC telegraphed the deal in April when it signed up to port some science apps to Knights Ferry, the 32-core MIC prototype platform. They subsequently built a small cluster outfitted with Knights Ferry coprocessors and started kicking the tires. Apparently that went well enough to warrant the 8 petaflop buy-in.
NVIDIA managed to garner some token approval in the Stampede project. A hundred or so of its next-generation Kepler GPUs will be hooked into some of the nodes, but mostly to be used for remote visualization. There are also a couple of NVIDIA GPUs attached to each of the 16 nodes of Stampede's big memory sub-cluster for data analytics-type workloads.
But the lion's share of the supercomputer's computational horsepower will come from Intel silicon. In addition to the 8 petaflops of MIC, 2 petaflops will be supplied by the upcoming Sandy Bridge CPUs, the 8-core Xeon E5, which will power the main cluster of 6,400 dual-socket nodes. An additional 5 petaflops of second-generation MIC coprocessors will be added in a couple years.
Knights Corner is going to have upwards of 50-cores and deliver something north of 1 teraflop of double precision number crunching performance, which should more or less match the new Kepler GPUs. The new NVIDIA parts are slated to arrive sometime in 2012, and it looks like volume production for Knights Corner won't start until 2013. I don't know how much of difference that will really make, especially in light of the choice TACC and the NSF just made.
Intel has more than 100 partners right now running their codes on the prototype MIC processors. The early returns appear to be positive, especially in regard to ease of programming. The x86 manycore architecture lends itself well to OpenMP-style programming, which gives it a built-in HPC customer base.
That's something NVIDIA didn't have when it began its GPGPU push into HPC in 2006. The GPU maker had to invent the CUDA software framework and then bring developers on board, which it managed to do quite successfully over the last five years. Intel, with its OpenMP-friendly architecture, will allow many HPC developers to leapfrog much of that onerous software transition phase.
Intel is pushing hard into HPC right now, noting opportunities like Stampede to sell barrels of chips with a single deal. But there is also the general feeling that the HPC market is an insatiable beast for high-powered processors. In a blog posted on Thursday by Joe Curley, Intel Director of Technical Computing, he lays out the rationale for Intel's high performance computing enthusiasm:
Last week at the Intel Developer Forum, Kirk Skaugen, VP and GM of Intel’s Data Center and Connected Systems Group, talked about the huge growth that is expected in HPC in coming years. (For those who didn’t have a chance to attend IDF you can see video of Kirk’s presentation here -> part 1 & part 2). Our estimations show that by 2015, the world’s top 100 supercomputers will be powered by 2 million CPUs and by 2019 this number will reach 8 million CPUs. To give you a perspective, in 2010, Intel shipped about 8 million server processors in total.
That's a rather compelling incentive for any chipmaker to be in the HPC business.
Posted by Michael Feldman - September 22, 2011 @ 6:01 PM, Pacific Daylight Time
Michael Feldman is the editor of HPCwire.
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