June 20, 2011
FREMONT, Calif. & HAMBURG, Germany, Jun 20, 2011 -- ISC 2011 -- SGI, a trusted leader in technical computing, today announced plans to deliver next generation supercomputers with Intel(R) Many Integrated Core (MIC) architecture, based on Intel(R) x86 architecture, and announced a strategic development partnership with Intel Corporationnto deliver such systems.
For too long, petaflop (defined as one thousand trillion floating point operations per second) computing has been reserved for the top 10 organizations in the world. Today's announcement is designed to drive wide industry adoption of petaflop computing, as well as take a quantum step forward towards exascale computing. Integrating Intel(R) MIC architecture into future SGI(R) Altix(R) ICE servers is expected to result in the following* computing breakthroughs:
-- Up to 10X increase in compute density
-- Up to 7X decrease in power per flop
Intel(R) MIC architecture features many small, low-power cores and familiar programming standards, and is expected to extend aggregate performance across the die to enable faster analysis of more complex data sets and compute problems.
"SGI recognizes the significance of inter-processor communications, power, density and usability when architecting for exascale," said SGI CTO Dr. Eng Lim Goh. "The Intel(R) MIC products will satisfy all four of these priorities, especially with their anticipated increase in compute density coupled with their familiar x86 programming environment."
SGI has a long history of bringing accelerators into its platforms to solve the world's most complex compute problems. As the size of applications continues to increase, accelerators provide alternatives from the perspective of density and performance per watt. A key part of its exascale strategy, integration of Intel(R) MIC architecture allows SGI to offer acceleration options that alleviate the need to learn and port to a different development environment. Intel(R) MIC technology also allows legacy codes to quickly enjoy the benefits of its architecture.
"Intel(R) MIC architecture is designed to address one of the biggest HPC and future exascale computing challenges -- software compatibility and ease of programming for fast processing of highly parallel applications," said Anthony Neal-Graves, Intel vice president and general manager, Many Integrated Core (MIC) Architecture. "Intel is pleased to have SGI, the company with a rich history of innovation in service of the HPC industry, as a partner in bringing MIC technology to the marketplace. This recognizes Intel(R) Many Integrated Cores architecture as a future solution addressing the needs of HPC community."
Note to Editors
SGI is showing an Intel(R) MIC architecture demo in its own booth #330 and in Intel booth #530 at the International Supercomputing Show (ISC) in Hamburg, Germany, taking place June 19-23, 2011.
SGI, a trusted leader in technical computing, is focused on helping customers solve their most demanding business and technology challenges. Visit www.sgi.com for more information.
*Performance results are based on a comparison of Intel(R) Xeon(R) 5600 processor series, 130W chip, in a current SGI(R) Altix(R) ICE 8400 system configured with 6400 nodes to projected future SGI systems containing both Intel Architecture and Intel MIC architecture.
Connect with SGI on Twitter (@sgi_corp), YouTube (youtube.com/sgicorp), and LinkedIn.
(C) 2011 SGI. SGI and Altix are registered trademarks or trademarks of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other countries. All other trademarks are property of their respective holders.
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?