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AMD Splits Server Platform


Starting in 2010, AMD will begin a new Opteron strategy that is based on two distinct server platforms: the Maranello (G34 socket) and the San Marino (C32 socket). Maranello is the one AMD has been talking about for some time, and until yesterday, was assumed to be the one and only platform that would carry the Opteron torch into the next decade. But apparently AMD plans to carry two server platforms into the future. In essence, they reflect the performance-versus-value dichotomy AMD sees in the marketplace.

The two platforms will map to separate Opteron processor families: the 6000 series for Maranello and the 4000 series for San Marino. The first chips to land on Maranello will be the 8- to 12-core Magny-Cours in 2010, followed by the 12 to 16-core Interlagos chips in 2011. Meanwhile, San Marino will get the 4- to 6-core Lisbon in 2010 and 6- to 8-core Valencia in 2011. Apparently, the 6-core Sao Paulo chip has disappeared from the roadmap.

As such, Maranello will represent the company's high-end server platform for two- and four-socket systems using the brawniest Opterons, while San Marino will be the economy platform for one- and two-socket systems using CPUs with lesser core counts. AMD has characterized these platforms in a slightly more flattering way, with Maranello aimed at applications requiring "performance and expandability," while San Marino is the choice for "power, efficiency and value."

The immediate question that popped into my head was: Which one is aimed at high performance computing? From AMD's perspective, the answer is both of them. The company lists virtualization, databases and HPC as application areas for Maranello, while file & print, email, virtualization, Web, cloud and HPC are designated for San Marino (note that virtualization turns up on both platforms too).

In practice, though, I suspect Maranello will be the choice for most OEMs that build servers for the HPC submarket. It supports four channels of DDR3 memory and up to 12 DIMMs, while San Marino tops out at two channels and four DIMMs. On the other hand, the two-channel, four-DIMM arrangement potentially delivers better overall memory performance since the channels-to-DIMM ratio is better. It may just be a matter of weighing the tradeoffs of a scaled-up (Maranello) versus scaled-out (San Marino) system.

In any case, I kind of like AMD's strategy here. The company has always been focused on balancing memory performance with compute power, so it's no real surprise it splits its platform just at the point that processor core counts are likely to diversify for different application areas. The realization that memory performance is almost impossible to scale under a single platform makes life more complicated for AMD. But it also allows the company to design CPUs with better assumptions about how they're going to be used in the field.

I'm also guessing that at least part of the decision to diversify the roadmap was a result of AMD's conclusion that it couldn't outrun Intel silicon. As AMD did in 2005 with the introduction of the K8 Opteron architecture that brought integrated memory controllers and the Direct Connect Architecture, the company is once again trying to out-maneuver its larger rival with a more balanced design.

Of course that doesn't mean AMD won't try to outgun Intel chips when it sees an opportunity. Along with the platform news, the company also announced it was launching its 6-core Istanbul processor a few months ahead of schedule, with OEMs expected to start shipping machines with the new chips in June. Since Intel's only 6-core Xeon is the Dunnington chip, based on the older front-side bus architecture, this was a way to muddy the waters a bit after Intel's launch of its quad-core Nehalem chips. Intel's 8-core Xeon, Nehalem EX, is getting primed for launch, but isn't expected to show up until early 2010. At that point, AMD could have its 8-core Magny-Cours ready to go.

Posted by Michael Feldman - March 29, 2010 @ 1:47 PM, Pacific Daylight Time

Michael Feldman

Michael Feldman

Michael Feldman is the editor of HPCwire.

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