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Blog: From the Editor

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Petascale Supers Poised for Debut in Asia


A couple of news items this week point to the rise of Asian aspirations for petaflop computing. The developments are taking place in Singapore and China, two regions that are trying to catch up to the US and Europe in supercomputing prowess and establish themselves as hubs for scientific R&D.

On Tuesday, Fujitsu and Singapore's (A*STAR) Institute announced they are developing a range of scientific applications for petascale computing, including biomedical, engineering and computation science codes. A*STAR, which stands for the Agency for Science Technology and Research, runs the Institute of High Performance Computing (IHPC), a national research institute aimed at advancing science and engineering via HPC technologies.

The application work is apparently in anticipation of a petaflop system built with Fujitsu PRIMERGY BX900 blade servers. Introduced in May of 2009, the BX900 blades are based on the latest Intel Xeon 5500 (Nehalem) processors, and not the SPARC64_VIIIfx processor (Venus) that Fujitsu developed for Japan's next-generation multi-petaflops supercomputer.

The press release is a somewhat vague about the eventual power and size of the A*STAR system. The only deployment mentioned is that of a 35 teraflop machine, which is a long way from a petaflop:

[T]he team will harness the compute power of Fujitsu supercomputer system comprising a cluster of Fujitsu PRIMERGY BX900 blade servers with a peak performance of over 35 teraflops and 91.8% efficiency with LINPACK program. This is the first installation of a Fujitsu PRIMERGY BX900-based supercomputer outside of Japan. This system, housed at A*STAR's Computational Resource Centre (A*CRC) at Fusionopolis, will be amongst the top tier of supercomputer sites in the world and the most powerful in Southeast Asia.

The second item comes from an article in Technology Review, which reports that the the Dawning 6000, a petaflop-capable supercomputer, will be based on China's third-generation Loongson CPU. If you'll remember, the 223 teraflop Dawning 5000a deployed in Shanghai was originally supposed to house Loongson chips, but switched to AMD Opterons when it became apparent the Chinese chips weren't ready for prime-time.

The Loongson CPU is based on the MIPS architecture, although this latest generation processor slated for the Dawning 6000 will also include hardware translation for x86 instructions. (The most recent HPC machines based on the MIPS processor architecture were offered by SiCortex, the now-defunct cluster vendor that ran out of funding in 2009.) A quad-core version of the Loongson chip is already in production, but apparently the Dawning super will get a performance charge from four "GStera" coprocessors designed to accelerate floating point operations.

Supercomputer maven Jack Dongarra adds his two cents:

Dongarra cautions that it's pointless to speculate about the performance of the forthcoming Dawning 6000 until benchmarks have been run, not least because the MIPS architecture is nonstandard in high-performance computing. "While I wish them well, I see a lot of challenges to making the whole system work, " says Dongarra. These challenges include having to adapt the software that Dawning runs.

The system could be ready to go as early as the end of 2010.

Posted by Michael Feldman - January 19, 2010 @ 2:26 PM, Pacific Standard Time

Michael Feldman

Michael Feldman

Michael Feldman is the editor of HPCwire.

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