October 05, 2009
Before Bill Dally joined NVIDIA as its chief scientist earlier this year, he had already enjoyed a long and accomplished career in academia, first at Caltech, then MIT, and finally at Stanford University. Along the way, he published over 200 research papers, and authored two textbooks, and collected IEEE's Seymour Cray and ACM's Maurice Wilkes awards.
But it wasn't just about teaching and research. At heart, Dally is an architect and developer of parallel computing technology and holds over 50 patents in the field. While at Caltech, he designed the MOSSIM Simulation Engine and the Torus Routing chip. Later at MIT he developed two experimental parallel computer systems, the J-Machine and the M-Machine. His last 12 years have been spent at Stanford, where he helped develop the system architecture and networking technology found in most large parallel computers today. He also cofounded two commercial ventures: Velio Communications Inc., a company that built high performance communications chips (and which was later acquired by LSI); and Stream Processors Inc., a fabless semiconductor firm that offers parallel processors for embedded markets.
Over the past three years, NVIDIA's move into the GPU computing space found resonance with Dally's lifelong interest in parallel computing. In January of this year, NVIDIA CEO Jen-Hsun Huang enticed him to come work for the company as its new chief scientist. By then, NVIDIA's future GPU architecture, Fermi, was already well into its development, giving Dally a clear indication of where the company was investing its future.
I got a chance to speak with Dally last week at the GPU Technology Conference in San Jose, California, and asked him why he chose to move from academia to NVIDIA, the significance of the Fermi architecture, and the future of GPU computing.
HPCwire: Bill, what drew you to come work for NVIDIA?
Bill Dally: That's a good question. In many ways, I sort of had the dream job: a professor at Stanford, with brilliant colleagues and students around, and interesting problems to work on. But over a series of conversations with Jen-Hsun, he convinced me that it was a compelling opportunity to come here and define, not just the future of GPUs, but the future of computing as a whole. That just seemed like too exciting a thing to pass up.
HPCwire: Let's jump into some of the news announced at the conference. The big announcement, of course, is Fermi, the new GPU architecture NVIDIA unveiled here. You've been talking quite a bit about it this week. How much were you involved in Fermi work?
Dally: Very little. I was actually involved in the architecture of the G80, as a consultant back in 2003. But by the time I joined the company in January, the architecture was largely done, and it was in the implementation phases. I did get involved in some implementation and circuit issues with Fermi. In particular, there were synchronizers that I helped to further improve the performance of, in collaboration with some of the circuit designers at NVIDIA.
HPCwire: There has already been a lot of talk about Fermi's impact on high performance computing. What do think will be Fermi's effect on supercomputing, from the low end to the high end, over the next couple of years?
Dally: I think it's going to be huge. We're in a situation -- I talked about in my session yesterday -- where GPU computing is at the tipping point. We already have the work of the pioneers, who have already gone to tremendous effort getting numerous applications -- fluid dynamics applications, solid mechanics applications, analysis of genomic sequences, analysis of neural models -- running on GPUs with tremendous speedups. We've seen 40x to 200x speedups over CPU performance and tremendous power savings. But it really hasn't been the mainstream solution for high performance computing. It's been in the niche.
I think there are really two main reasons for that: double precision performance and ECC. When we would go and talk with customers who wanted to build really large clusters, the ECC issue would always come up. They said if you want to build mission-critical applications, if you want to build a large cluster, it has to have ECC, or you can't play with the big boys. Obviously we listened to that, and Fermi has ECC.
If you look at the one area where GPU computing has really taken off so far, it's oil and gas exploration -- for both seismic analysis and reservoir simulation. I think a big reason why that is one of the first areas to take off is because it can make very good use of single precision.
We heard how Bloomberg used GPUs for their bond pricing. Even though that's a double precision application, they were able to get enough gains from the GT200, which has just one-eighth the double precision performance of Fermi. Now we've basically taken care of the two big obstacles for everybody.
When we start talking to people who want to build a huge cluster for the top one or top 10 of the TOP500 list, and they say, "We need to make it fit in this power envelope. We can't do that with CPUs." And they say, "What are the other alternatives?" Even with something like a Cell [processor], they can't do it. The only way they can really do this is with GPU computing. I think we're really poised for GPU computing to become the standard way of doing high performance computing.
The real rate limiter here is going to be porting of codes. It's going to be limited by how people can take important codes and move them over to run on the GPU.
HPCwire: At one of the sessions here at the conference, there was talk about exaflop computing, a milestone which we're supposed to hit in about nine years. Do you think GPU computing is going to be an integral part of that?
Dally: I think GPU computing is going to be the central part of any serious exascale effort. I was actually an author of that exascale report that [Cray CTO] Steve Scott had in his presentation. The reason is that -- and Jen-Hsun made this point really well in his keynote presentation -- GPUs are throughput computers. They're optimized to deliver performance per dollar, per unit power, and per unit area for [applications] with plenty of parallelism.
In contrast, CPUs optimize for latency. They spend a lot of die area and a lot of power optimizing single thread performance and doing speculative computation: predicting branches and so on. All of that costs area and power, and doesn't give you more FLOPS.
To get to exascale, it's all about FLOPS per watt. It's all about how efficiently you can perform computations, and GPUs are optimized for FLOPS per watt. They are the ideal throughput computer. Over time, they are going to evolve from their current position of being graphics devices that people are using to do computing to being really awesome throughput computing devices that can do both computing and graphics very well.
HPCwire: Is NVIDIA committed to the GPU-as-coprocessor model for the foreseeable future, or are you guys starting to think about integrating a sequential processor in the GPU at some point?
Dally: At some point that may make sense. If you look at today though, nobody's asking us to make slower GPUs. Integration is an economic decision. The question is if it's cheaper to put two functions on one chip or is it cheaper and more flexible to have two separate chips. And the answer today is that it's more flexible to have two separate chips. With the ability to have a single address space that we provide, it doesn't really matter which chip the CPU or the GPU are on. You want to have the bulk of the memory on the GPU side, so that you can be doing your calculations there. The time to launch threads is not limited by the PCIe connection. It may be limited a little by the driver software on the CPU, but integrating that on-board wouldn't reduce that overhead in any substantial way.
So the only argument would be: "At what point in time would you be willing to carve out some die area, and make your GPU slower, and limit the flexibility of what GPUs you could match with CPUs to get the economic benefits of integration?" We don't see that happening yet -- at least at the high end.
At the low end, we do in fact do exactly that. Our Tegra product incorporates a GPU, a number of fixed function accelerators, and two ARM cores to make a really compelling system on a chip for mobile applications. At that low end of the spectrum, people don't need the fastest possible GPU. But they do need an integrated solution that reduces the cost, the power, and the form factor. For mobile applications, all three of those features are critical, but for the high end parts, that's not in the cards for the near future.
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?