August 27, 2009
The latest and greatest chippery was on exhibit earlier this week at the Hot Chips conference, an IEEE-sponsored event that encourages microprocessor vendors to talk about their next generation silicon. The emphasis is on high performance chips, so a lot of the products and technology presented at the conference eventually end up in the hands of supercomputing users. While I didn't attend the event myself -- my wife discourages me from going to any out-of-town conferences with the word "hot" in them -- I did make a point of following the proceedings from afar.
The star of the show this year was the upcoming Power7 processor being developed by IBM. This is the chip that will be powering NCSA's "Blue Water" supercomputer, a 10-petaflop machine slated for deployment in 2011. Blue Waters will be the first production deployment of IBM PERCS, a set of technologies that is being partially funded by DARPA under its High Productivity Computing Systems (HPCS) program. For more pedestrian uses, the Power7 will also be used in IBM's Power 5xx server line. The new chips should show up in IBM gear sometime in 2010.
The 45nm Power7 will come in four-, six-, and eight-core variants, and can execute up to four threads per core. Two dual-channel DDR3 memory controllers are integrated onto the chip, delivering an impressive 100GB/sec of memory bandwidth. IBM is claiming the chip's raw performance is on the order of two to four times that of the Power6, but will consume about the same amount of power. No one is talking specifics in regard to clock speeds yet, but the first crop of Power7 processors will almost certainly have slower clocks than the current top-of-the-line 5.0GHz Power6 parts.
Besides increased core and thread count, probably the biggest new feature of the Power7 is the use of embedded DRAM (eDRAM) for on-chip L3 cache. This is the same technology that has been incorporated into IBM's Blue Gene PowerPC ASICs for years in both Blue Gene/L and Blue Gene/P. Since eDRAM requires just one transistor per device, as opposed to six transistors for static RAM (SRAM), eDRAM takes up only a third as much space. Plus it draws only a fifth of the power of SRAM.
The result is that more L3 cache can be placed on-chip in order to help minimize main memory accesses -- an increasingly important feature as core counts rise. In the case of the Power7, the designers opted for 32 MB of L3. For comparison, Intel's upcoming 8-core Nehalem EX chip has 24 MB of L3, while AMD's 12-core Magny-Cours chip will use just 12 MB.
Speaking of which, AMD supplied some additional details about its upcoming Magny-Cours Opteron silicon at the Hot Chips event. Apparently the CPU will be constructed from two six-core chip modules, mirroring Intel's initial approach to its first quad-core Xeons (that AMD was so critical of at the time). Compared to the current generation six-core Istanbul chips, Magny-Cours will have lower clock frequencies in order to keep within the same power and thermal envelope.
To help keep all 12 cores fed with data, the new design incorporates four HyperTransport links (compared to three in Istanbul) and a quad-channel DDR3 memory controller (compared to a two-channel DDR2 controller in Istanbul). AMD is planning to release the dozen-core wonder in Q1 2010. Presumably they'll start showing up in supercomputers in the same timeframe or shortly thereafter.
Not to be out-cored, Sun Microsystems was talking up its 16-core "Rainbow Falls" processor, the company's third-generation UltraSPARC T series (Niagara) chip. Sun says this latest version will run up to 128 total threads simultaneously. Compared to other server microprocessor designs, Rainbow Falls is a bit unconventional. For example, the Sun engineers have banished L3 cache. Instead the CPU relies on 16 banks of L2 cache plus four "coherency units" that are used to help optimize data synchronization between main memory and cache.
Since Rainbow Falls follows the Niagara lineage, presumably it will be targeted to high-throughput datacenter workloads, such as Web serving, rather than technical computing. Although the floating point unit has been pumped up, it was Sun's ill-fated "Rock" processor that probably had the best shot at supercomputing stardom. According to many reports, the company has pulled the plug on the Rock effort, leaving it without a high-end chip for scientific applications. To be sure, there's even a question whether Rainbow Falls will see service, given the pending Oracle acquisition of Sun and its uncertain support of Sun's hardware business. Nevertheless, the new chip is currently slated for its debut in 2010.
So with cores multiplying like rabbits on CPUs, what do we need GPUs for? At this year's Hot Chips event, the GPU contingent was relatively silent. No new graphics processors were presented, although NVIDIA CEO Jen-Hsun Huang did manage to rain on the CPU parade a little bit by drawing attention to the disparity between performance gains between the two major processor architectures. Huang predicted that over the next six years GPU compute power will increase by a factor of 570, while CPU architectures will only increase by a power of three. That seems like an awfully optimistic scenario for GPUs, and a rather pessimistic one for CPUs. In fact, in six years there may not even be a strict delineation between GPUs and CPUs. I guess we'll just have to wait for Hot Chips 2015 to see if anything we thought in 2009 was even remotely accurate.
Posted by Michael Feldman - August 27, 2009 @ 5:30 PM, Pacific Daylight Time
Michael Feldman is the editor of HPCwire.
No Recent Blog Comments
10/30/2013 | Cray, DDN, Mellanox, NetApp, ScaleMP, Supermicro, Xyratex | Creating data is easy… the challenge is getting it to the right place to make use of it. This paper discusses fresh solutions that can directly increase I/O efficiency, and the applications of these solutions to current, and new technology infrastructures.
10/01/2013 | IBM | A new trend is developing in the HPC space that is also affecting enterprise computing productivity with the arrival of “ultra-dense” hyper-scale servers.
Ken Claffey, SVP and General Manager at Xyratex, presents ClusterStor at the Vendor Showdown at ISC13 in Leipzig, Germany.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?