March 12, 2009
The global economic system may be collapsing, but quantitative financial analysis will endure. At least, that's what Kuberre Systems is hoping. Earlier this week, the Massachusetts-based firm launched HANSA (Hardware Accelerator for Numerical and Systems Analysis) , a new FPGA-based HPC platform intended to accelerate compute-hungry financial applications. The overall architecture is somewhat reminiscent of Convey Computer's HC-1, inasmuch as it virtualizes the FPGA resources from the application developer.
If you haven't heard of Kuberre before, that's because this is its first big push into high performance computing. The company's been around since 2001, primarily in the financial services arena, offering an array of investment management products and services. Its foray into HPC began a couple of years ago when it started thinking about a platform that could help quants speed up their risk analysis models. Kuberre settled on an FPGA-based architecture because of its flexibility and because of the company's familiarity with FPGA technology.
Despite the meteoric rise of GPGPU computing -- and to a lesser extent, Cell-based HPC -- over the last couple of years, FPGAs have offered some unique attributes for HPC. "Accelerators of all types are growing in acceptance and have great potential in HPC," notes Addison Snell of Tabor Research. "In particular, FPGAs seem well-suited to scalable applications that rely heavily on text or integer calculations, such as genomics, event processing in real-time data feeds, or ultra-scale business computing.”
Kuberre's HANSA can house from 1-16 FPGA boards, each one containing four FPGAs and 16 GB of memory. The FPGAs are Altera's Stratix II generation, and the company is already looking to upgrade the platform to the newer Stratix IV chips in the near future, which should provide about 50 percent greater computational capacity. A single dual-core x86 CPU on a separate board is used to run the OS -- either Linux or Windows -- and to talk with the outside world. The glue that ties the FPGA boards with the CPU is the APSC -- the Algorithmic Processing and Switching Complex, which manages the considerable data traffic in the system.
A fully loaded HANSA box containing 64 FPGAs and 256 GB of memory fits in a 9U enclosure, and runs about $500,000. No benchmarks are yet published for the machine, but when I spoke with Kumar Metlapalli, Kuberre's the CEO and founder, he said a 16-board system should hit at least 250 gigaflops on Linpack. According to the company's press release, when compared to traditional CPU-based HPC machines, a HANSA setup will do the equivalent work at "1/3 the cost, with 2 percent of the energy requirements, and in 1 percent of the floor space."
Thanks to the shape-shifting nature of FPGAs, the hardware can be configured as a cluster/grid of 768 "RISC" CPUs for a generic C/C++ programs, or as supercomputer with 1,536 double precision cores for FP-intensive numerical processing. The machine can also be split between some combination of the two.
The software stack consists of a set of C/C++ and Java APIs and what they call firmware building blocks. The building blocks present another set of APIs to access routines for ScaLAPACK operations, correlation matrices, interpolations, and Monte Carlo simulations. There's an additional API that allows developers to integrate data streaming operations. For example, for a financial application, real-time market data from a WOMBAT feed could be captured and passed on to other software for further number crunching.
Metlapalli says if a user's code is GNU compliant, they just have to recompile their C/C++ source for HANSA without making any modifications. These programs can then be run in concurrent fashion on multiple instances of the platform's virtual grid of CPUs. On the other hand, if the user wants to take advantage of data-level parallelism afforded by the FPGAs, API library calls (e.g., ScaLAPACK) will have to be inserted in the code.
There's an additional interface provided to partition the FPGA hardware into as many as 16 "contexts" for these different classes of operations. Again using the example of a financial application, a couple of FPGA boards could be devoted to capturing real-time market streams, while four other boards could be using ScaLAPACK for risk analysis, and a third set of boards could be doing Monte Carlo simulations for interest rate forecasts.
Besides financial services applications, Metlapalli says the architecture is well suited for bioinformatics searches and CFD. Beyond that, HANSA should be generally applicable to any app that has to deal with Eigen value problems, pattern recognition, image processing, and data encryption, to name a few. Again, the reconfigurable nature of FPGAs buys you quite a bit of versatility with applications.
Metlapalli says they've already seen some interest with HANSA from financial institutions on the buy-side (e.g., hedge fund firms) as well as sell-side (e.g., investment banks). Apparently, the U.S. DoD has also made some inquiries.
My first take on this is that it's a pretty compelling story, especially if you're willing to tap into the HANSA libraries that would take fuller advantage of the FPGAs. I think there's definitely room for both GPGPU, Cell acceleration, and reconfigurable computing in the HPC ecosystem, but this is a tough economic climate to introduce innovation that doesn't produce immediate bottom line savings in IT budgets. I hope companies like Kuberre can grab a few customer wins and help keep reconfigurable computing in the HPC mix.
Posted by Michael Feldman - March 12, 2009 @ 6:32 PM, Pacific Daylight Time
Michael Feldman is the editor of HPCwire.
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