December 16, 2008
Aggregation is a virtualization technique that makes multiple physical systems appear to function as a single logical system. The building blocks for this approach are the same building blocks used in scale-out (clustering): industry-standard servers and high-speed interconnects. Aggregation fundamentally replaces the functionality of custom and proprietary chipsets with software, leveraging commodity interconnects such as InfiniBand. It utilizes only a tiny fraction of the system's CPUs and RAM to provide chipset-level services without sacrificing system performance.
By running a single logical system, customers reduce the management costs associated with managing multiple cluster nodes, and take advantage of large contiguous memory and unified I/O architecture. To understand how aggregation works, we will first explain the architecture of a traditional SMP system, and then dive into the details of the aggregation approach.
Traditional Multi-Processor Systems
Traditional multi-processor systems run a single operating system (OS). The OS interacts with the system using a well-defined hardware interface, which provides the OS with predefined services to use and control the hardware. These interfaces may include hardware detection and probing, memory ordering semantics, I/O space access and interrupt delivery mechanisms.
Intel's Multiprocessor Specification allows a single copy of an operating system to run on a single CPU system as well as on a multi-CPU system with up to 255 CPUs. It details a well-defined interface that allows the OS to know exactly how to probe the hardware to determine what kind of system is running underneath it, and then behaves accordingly. This interface also handles the coordination of the underlying system with the OS. For a traditional multi-processor system, such interface is implemented in a silicon chipset.
In addition to the hardware interface, the multi-processor system consists of CPUs, memory and I/O subsystems. These components are all connected together with a proprietary backplane, often implemented by a chipset. Examples of such chipsets and backplanes are Intel's FSB (Front Side Bus), AMD's HT (Hyper-Transport), SUN's CrossBar, SGI's NUMALINK and IBM's XA.
The chipset and the proprietary backplane (system interconnect) are the elements where multi-processor systems differ the most from each other and where the major cost of a high-end multi-processor systems is derived. The system interconnect is expensive because the more processors that are added to a system, the more complex it becomes to connect them all together in a manner that ensures both coherency and performance. Traditional multi-processor systems require the creation of a custom chipset to implement the system interconnect to allow processor, memory and I/O communication.
Software Approach: Aggregation
Aggregation reduces the costs associated with custom chipsets and backplanes. It requires multiple high-volume, industry-standard x86 systems (processor speed and amount of memory across boards do not have to be the same). In addition, a high-speed, low-latency interconnect serves as backplane. InfiniBand infrastructure excels in this regard. The aggregation software is loaded on each system board below the operating system layer.
Once loaded into the memory of each of the system boards, the virtualization software aggregates the compute, memory and I/O capabilities of each system and presents a unified virtual system to both the operating system and the applications running above the OS. The aggregation software uses a software-interception engine in the form of a Virtual Machine Monitor (VMM) to provide a uniform execution environment. The software also creates the required BIOS and Advanced Configuration and Power Interface (ACPI) environment to provide the OS (and the software stack above the OS) a coherent image of a single system.
The software maintains cache coherency between the individual boards using multiple advanced coherency algorithms. These complex algorithms operate concurrently on a per-block basis, based on real-time memory activity access patterns. Board local-memory is leveraged together with caching algorithms to minimize the effect of interconnect latencies.
The virtualization software aggregates I/O resources across all boards into a unified PCI hierarchy and presents them as a common pool of I/O resources to the OS and the application. The OS is able to utilize all the system storage and networking controllers toward providing high-I/O system capabilities.
The Advantages of Aggregation
Ease of Use
Aggregation simplifies scale-deployments by having a single system to manage compared to the complexities involved with managing a cluster. A single system removes the need for cluster file systems, cluster interconnect provisioning, application provisioning and installation and updating multiple operating systems and applications. The use of one operating system instead of one per node results in a significant savings in time and money during installation, as well as in ongoing management costs.
Simplified I/O Architecture
I/O requirements for a scale-out model can be very complex and costly, involving networked storage with accompanying costs related to additional HBAs, and FC switch infrastructure. Aggregation technology consolidates each individual server's network and storage interfaces. I/O resource consolidation reduces the number of drivers, HBAs, NICs, cables, and switch ports and all the associated maintenance overhead. The user needs fewer I/O devices to purchase, manage and service with increased availability, resiliency and runtime scalability of I/O resources.
Large Memory System
For workloads that require a large contiguous memory, customers have traditionally used the scale-up approach. Aggregation provides a cost-effective alternative to buying expensive and large proprietary shared-memory systems for such workloads. It enables an application requiring large amounts of memory to leverage the memory of multiple systems, and reduce the need to use a hard-drive for swap or scratch space. Application runtime can be dramatically reduced by running simulations with in-core solvers or by using memory instead of swap for large-memory footprint models.
Aggregation thus provides a cost-effective virtual x86 platform with a large shared memory that minimizes the physical infrastructure requirements and can run both distributed applications, as well as applications requiring a large memory footprint at optimal performance on the same physical infrastructure.
Compute-Intensive, Large Core-Count Requirements
For workloads that require a high core count coupled with shared memory, customers have traditionally used proprietary shared-memory systems. Aggregation provides a very cost effective x86 alternative to these expensive and proprietary RISC systems.
Aggregation technology combines memory-bandwidth across boards, as opposed to traditional SMP or NUMA architecture where memory bandwidth decreases as the machine scales. This enables solutions based on aggregation technology to show close-to-linear memory bandwidth scaling, thereby delivering excellent performance for threaded applications.
Even in large cluster deployments in data centers, it makes sense to deploy aggregation, since fewer larger nodes mean less cluster complexity and better utilization of the infrastructure due to reduced fragmentation of the resources. An example can be found in the financial services industry, where organizations need to run hundreds or thousands of simulations at once. A common deployment model will involve hundreds of servers, where each will execute a few simulations. In this example, each cluster node is running a single application at 80 percent utilization. By using aggregation to create fewer larger nodes, every four aggregated systems can run another copy of the application, leveraging the underutilized resources and driving an additional 25 percent utilization.
ScaleMP's vSMP Foundation is an example of the aggregation concept. The company has taken an approach that makes a tradeoff between memory latency and memory bandwidth.
Memory Bandwidth vs. Memory Latency
vSMP Foundation uses caching technologies to provide parallel access to system memory. With vSMP Foundation, data migration and replication are employed to maximize system memory bandwidth. The additional system memory bandwidth is used to mask the backplane latencies. ScaleMP uses standard interconnect technology versus the custom built back planes used in traditional multi-processors. While the backplane latency of the InfiniBand interconnect is higher than traditional multi-processor backplanes, the additional memory bandwidth offsets this higher latency. One of the keys to appreciating vSMP Foundation's ability to mask backplane latency and provide superior performance is the understanding of the fundamentals behind efficiency in memory management. At its elemental level, efficiency can be defined as:
Efficiency = 1 – (Access x Latency)
Access represents the number of times a processor has to reach out to memory that is not within the processor cache (i.e., on main memory, requiring access via the backplane).
Latency represents the amount of processor wait time such memory requires each time it is accessed.
The efficiency of a system can be improved by reducing the number of times the processor accesses the backplane or reducing the latency of each access to the backplane. Typically, the access is defined by the nature of the application, and latency is based on the technology of the backplane.
Historically, the industry has improved performance by focusing significant R&D on reducing latency in each new generation of products (backplanes, memory-speed, etc.). The assumption was that the access patterns were driven by the applications and, hence, largely out of the control of the system vendors.
ScaleMP's basic approach was to replace proprietary chipsets and backplanes with InfiniBand interconnects and reduce the number of times a processor has to access the backplane for memory operations on another physical board.
Non-Uniformed Memory Architecture (NUMA) is a common multi-processor architecture which inherently support system scaling by adding additional system nodes. NUMA drawbacks are result of non-homogenous memory access latency, which require operating system and application awareness. ScaleMP utilizes a combination of NUMA and Cache Only Memory Architecture (COMA) in conjunction with a massive cache (typically 5-10 percent of the system's RAM), to trade off the backplane latency with the use of redundant RAM for caching. The backplane latency is mitigated using software-driven adaptive caching techniques and achieving better systems economics by leveraging commodity memory costs versus proprietary backplanes and chipsets.
ScaleMP utilizes multiple memory coherency algorithms that are selected based on several aspects of the application behaviors, such as historical memory access pattern, on-the-fly code analysis and I/O behavioral analysis. In essence, in spite of having higher backplane latency versus traditional multi-processor systems, vSMP Foundation techniques for memory access reduction are designed to offset the disadvantage of higher-latency, commodity industry-standard interconnects. With the progress that InfiniBand is making in improving latency from SDR to DDR to QDR, the latency gap between an InfiniBand interconnect and a proprietary interconnect is shrinking.
By leveraging industry-standard processors and systems coupled with industry-standard interconnects, aggregation creates a new paradigm for high performance computing and represents a step toward delivering better performance with lower cost and less complexity. Aggregation overcomes the fundamental limitation of clusters for applications that require large shared memory, and it addresses the barriers many technical computing customers have when it comes to adopting clusters, namely a lack of appropriate IT skills to install and manage them. The drawbacks associated with traditional SMP systems, such as high cost and vendor lock-in, are likewise avoided.
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