December 11, 2008
Between Intel, Microsoft and a host of smaller firms, there's been some hopeful progress on software for multicore processors. But even if we manage to develop multicore-smart apps, we have to remind ourselves that the memory wall looms ahead. Despite the stall in CPU clock speeds, the proliferation of cores is continuing to widen the gap between microprocessor performance and memory performance.
The problem is not new, certainly not to old-time techies. The classic missive on the memory wall (PDF) was written in 1994 by researchers Wulf and McKee at the University of Virginia. They concluded that we were headed for disaster in the near future -- in 10 years or so. Fortunately, they didn't take into account that cache memory would grow in both size (KB to MB) and sophistication (three levels, prefetching, etc.). Also, integrated memory controllers would become the norm, helping to improve DRAM access.
But the fundamental hardware realities remain. The bandwidth and latency of main memory (static DRAM) have not kept pace with CPU performance. Currently, processor caches provide access to data with latencies of around one or two nanoseconds, while DRAM latencies are roughly 100 times as large. Bandwidth, likewise, is reduced as you move from cache to main memory. Eventually an application generates a cache miss and the processor stalls, twiddling its bits for a 100 cycles or more until the data is retrieved from (or sent to) main memory. Even an L3 cache access costs tens of processor cycles.
For HPC, the memory wall is bigger and closer than it is for other computing domains. Data-hungry, compute-intensive applications place big demands on the memory subsystem. A recent article in IEEE Spectrum spotlights a study at Sandia that simulated HPC application performance with increasing core counts:
With no other way to improve the performance of processors further, chip makers have staked their future on putting more and more processor cores on the same chip. Engineers at Sandia National Laboratories, in New Mexico, have simulated future high-performance computers containing the 8-core, 16-core, and 32-core microprocessors that chip makers say are the future of the industry. The results are distressing.
Indeed. In a graph that looks somewhat reminiscent of this year's NASDAQ stock chart, the Sandia simulation predicts that for certain types of HPC applications, performance rises modestly from two to four cores, and even more modestly from four to eight. But after eight cores, performance actually drops off, and goes into free-fall beyond 16 cores.
The implied knock on multicore seems somewhat misplaced. If the simulation were performed on a single-core processor with increasing clock speeds, presumably you would see the performance increase in a similar manner as you doubled and quadrupled the clock frequencies, with the memory bottleneck exerting its braking effect. At some point though, the performance would just level off as the CPU hits the memory wall.
Theoretically splitting up computation across multiple cores should help mitigate the memory wall effect since there's a decent chance that some cores will still be happily running in cache, while others are stuck waiting for data from main memory. But the Sandia study predicts decreasing performance above eight cores, so something analogous to Fred's Brooke's "Mythical Man-Month" must be going on. In that model, adding additional resources slows down the process, mainly because of additional overhead in communication. It's Moore's Law versus Brooke's Law, with the latter trumping the former.
The category of HPC applications that the Sandia engineers were studying is what they call "informatics" -- a catch-all they use to describe compute-intensive codes that are searching for patterns in very large databases. Applications used to help with natural disaster management and counterterrorism fall into this category. Unlike the more predictable data access patterns of HPC codes that model a physical system, like a hurricane or an oil reservoir, informatics apps tend toward irregular access. Spatial and temporal locality are lower in these types of codes and that puts a strain on the whole memory hierarchy.
The extent to which memory bandwidth and latency is limiting HPC performance overall is largely unknown, although anecdotal evidence suggests a growing problem. At SC08 last month, IDC reported that users are hitting the wall with multicore. If that's a generalized situation, it's going to get worse fast.
According to an April 2008 HPC User Site Census report by Tabor Research, the installed base of HPC systems is only about midway into its transition from single-core to multicore, with single-core CPU chips currently making up more than half of total processors. That was eight months ago, so we already may be past the tipping point. The report concludes the transition to multicore should be mostly completed within the next few years. That will happen if for no other reason than you won't be able to buy single-core processors. Intel's last one-core server chip was released over three years ago.
And while the report states that memory per core is trending upward -- from 1.36 GB/core in pre-2005 systems to 2.96 GB/core in systems deployed in the first quarter 2008 -- the memory wall is not a capacity issue. In some cases more memory will translate into more aggregate bandwidth, but adding additional DRAM is usually done to avoid the even more daunting I/O wall at the disk.
It would be an interesting exercise to track cache size per core in deployed HPC systems, since larger caches have been the biggest defense against the memory wall. Cache has been growing exponentially to try and keep up with the multiplying cores. The latest Shanghai quad-core Opteron chips from AMD have 6 MB of L3 cache, as well as 2 MB of L2 and 256 KB of L1. The corresponding Harpertown processor from Intel has up to 12 MB of L2 and 128 KB of L1 (but no L3). The more cache-heavy four- and six-core Dunningtons have 6 MB of L2 and up to 16 MB of L3, along with 96 KB of L1 per core.
In the long-term, the scaling of the memory wall may take place once 3D memory devices and/or optical interconnects are commercialized. Failing that, expect to see much larger and smarter cache hierarchies.
Posted by Michael Feldman - December 10, 2008 @ 9:00 PM, Pacific Standard Time
Michael Feldman is the editor of HPCwire.
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