Parallel Thoughts

By Michael Feldman

September 28, 2007

As Intel and AMD take a break from beating each other about the quads, this week we’ll turn our attention to software — specifically, parallel programming. Yes, multicore processors, GPUs and FPGAs are all the rage; but without applications to run on them, they’re just pretty etchings. In this week’s issue we have three articles that discuss different software approaches to getting the most out of the new hardware.

In our first feature article, RapidMind Chief Scientist Michael McCool makes a case for data parallelism — not surprising, considering his company’s platform is all about exploiting that particular aspect of HPC applications. McCool’s contention is that traditional task parallelism is of only limited use, since this model is difficult to scale to the levels necessary for today’s multicore systems, much less the manycore systems of the future. The main problem here is that the memory bottleneck demands much more latency tolerance than can be achieved by the relatively low numbers of tasks that can be naturally teased out of a typical application.

Says McCool: “The solution to this dilemma is data parallelism. In data parallelism, the structure of the data is used to drive the creation of more and more parallel tasks as needed. Since larger problems with more data naturally result in more parallel tasks, a data-parallel approach results in a scalable solution that can automatically take advantage of more and more cores.”

McCool does make an important distinction between SPMD (Single Program, Multiple Data) parallelism and SIMD (Single Instruction Multiple Data) parallelism. The former is the more versatile, inasmuch as it avoids the latter’s limitation of relying on a single operation per data stream. In essence, SIMD implies vector processors, while SPMD can be applied to a variety of architectures.

In “Language Design for an Uncertain Hardware Future,” The MathWorks’ Rod Lurie contends that the implementation language should be selected with the domain expert in mind. The idea is that language should enable users to develop applications as quickly as possible, without having to worry about the target architecture. He suggests programmers take a two-pass approach to software development. In the first pass, they should concentrate on getting the algorithm correct, and not be concerned with performance issues. In the second pass, the programmer can go back and insert parallelism to optimize runtime execution. But the language system itself should be responsible for mapping the parallelism onto the underlying hardware.

According to Lurie: “In this two-pass model, domain experts, like the scientists and engineers who will be major consumers of high performance computing systems, should be able to express their ideas in a natural way, allowing them to explore their solution space rapidly. To maximize their productivity, these experts should be able to focus on their core competencies.”

The second pass is accomplished by annotating the original algorithm with parallel constructs, like PARFOR, MATLAB’s method of specifying parallel for-loops. Parallel annotation usually has the advantage of being compatible with non-parallel hardware. In other words, the parallel constructs will just be ignored when executed on a single-core platform.

To round out our trio, Visual Numerics’ Tim Leite writes about some of the difficulties of porting applications from legacy systems to clusters. The advantages of porting are obvious, but the obstacles can be formidable and include preserving elements like computational accuracy and portability. Multiple language support also can become a big issue when migrating software to a new platform. Leite suggests that using commercial numerical libraries to insulate the application from the underlying hardware can help to ease some of these porting pitfalls. He also notes that these same libraries often give the developer some specific support for MPI programming.

Writes Leite: “As compute clusters become more prevalent and powerful, computational libraries continue to evolve to assist the developer in leveraging the cluster technology. Building parallel processing-enabled applications can be difficult, and commercial libraries can help programmers avoid some of the issues associated with optimizing code for a cluster. In fact, some libraries have introduced techniques that assist not only the sophisticated programmer, but also the novice distributed computing developer.”

While each of the three approaches reflects the particular vendor’s offerings, they all have some important elements in common. One is the realization that existing commercial toolchains can be harnessed. Although the APIs in the vendor solutions are proprietary, they leverage standard language environments. For example, The RapidMind platform is built around a C++ framework and can take advantage of the large ecosystem of tools, libraries and applications that has grown up around that language. The MathWorks is fortunate to have its very own and very popular MATLAB language. It was originally developed with a single processor in mind, but the Distributed Computing Toolbox was added in 2004 to help users adapt their code for the emerging generation of parallel hardware. And finally, Visual Numerics’ IMSL libraries are written in the some of the most widely used languages today: C, C#, Java and Fortran. Almost without exception, commercial parallel software products are built on top of well-established languages.

Each software approach discussed here also pays a good deal of attention to maintaining portability across targets. Since application development has become one of the most severe bottlenecks in system deployment, any technology that can decouple the code from the hardware is greatly appreciated. With the recent proliferation of multicore processors, accelerator coprocessors and cluster architectures, there is a real motivation to make sure the software developer (and end-user) is insulated as much as possible from hardware concerns. RapidMind’s solution is perhaps the most ambitious in this regard. It’s designed to map application code to x86 CPUs, a number of GPUs, or the Cell processor.

Related to portability is scalability. Today’s clusters come in many sizes, from a few nodes to thousands. At the level of the processor, chipmakers are using Moore’s Law to double the core count every couple of years. If applications aren’t developed with scalability in mind, the code’s longevity will be tied to the hardware it was originally targeted for. In the brave new world of parallel architectures, the ability to automatically scale software is a necessity.

Admittedly, none of the current approaches to deal with parallel programming is without drawbacks. For one thing, each tends to focus on a single dimension of parallelism, usually either at the level of the processor or at the level of the cluster. And Lurie himself acknowledges that his two-pass model would be unnecessary if the underlying language had built-in intelligence to implicitly perform parallelization. Forcing the software writer to think in parallel is the single biggest obstacle to large-scale development of parallel codes. Today unfortunately, there are no magic bullets because there is no magic gun. A more general framework awaits.

—–

As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at [email protected].

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion XL — were added to the benchmark suite as MLPerf continues Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing power it brings to artificial intelligence.  Nvidia's DGX Read more…

Call for Participation in Workshop on Potential NSF CISE Quantum Initiative

March 26, 2024

Editor’s Note: Next month there will be a workshop to discuss what a quantum initiative led by NSF’s Computer, Information Science and Engineering (CISE) directorate could entail. The details are posted below in a Ca Read more…

Waseda U. Researchers Reports New Quantum Algorithm for Speeding Optimization

March 25, 2024

Optimization problems cover a wide range of applications and are often cited as good candidates for quantum computing. However, the execution time for constrained combinatorial optimization applications on quantum device Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at the network layer threatens to make bigger and brawnier pro Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HBM3E memory as well as the the ability to train 1 trillion pa Read more…

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HB Read more…

Nvidia Looks to Accelerate GenAI Adoption with NIM

March 19, 2024

Today at the GPU Technology Conference, Nvidia launched a new offering aimed at helping customers quickly deploy their generative AI applications in a secure, s Read more…

The Generative AI Future Is Now, Nvidia’s Huang Says

March 19, 2024

We are in the early days of a transformative shift in how business gets done thanks to the advent of generative AI, according to Nvidia CEO and cofounder Jensen Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

Nvidia Showcases Quantum Cloud, Expanding Quantum Portfolio at GTC24

March 18, 2024

Nvidia’s barrage of quantum news at GTC24 this week includes new products, signature collaborations, and a new Nvidia Quantum Cloud for quantum developers. Wh Read more…

Alibaba Shuts Down its Quantum Computing Effort

November 30, 2023

In case you missed it, China’s e-commerce giant Alibaba has shut down its quantum computing research effort. It’s not entirely clear what drove the change. Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

Shutterstock 1285747942

AMD’s Horsepower-packed MI300X GPU Beats Nvidia’s Upcoming H200

December 7, 2023

AMD and Nvidia are locked in an AI performance battle – much like the gaming GPU performance clash the companies have waged for decades. AMD has claimed it Read more…

DoD Takes a Long View of Quantum Computing

December 19, 2023

Given the large sums tied to expensive weapon systems – think $100-million-plus per F-35 fighter – it’s easy to forget the U.S. Department of Defense is a Read more…

Synopsys Eats Ansys: Does HPC Get Indigestion?

February 8, 2024

Recently, it was announced that Synopsys is buying HPC tool developer Ansys. Started in Pittsburgh, Pa., in 1970 as Swanson Analysis Systems, Inc. (SASI) by John Swanson (and eventually renamed), Ansys serves the CAE (Computer Aided Engineering)/multiphysics engineering simulation market. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Intel’s Server and PC Chip Development Will Blur After 2025

January 15, 2024

Intel's dealing with much more than chip rivals breathing down its neck; it is simultaneously integrating a bevy of new technologies such as chiplets, artificia Read more…

Baidu Exits Quantum, Closely Following Alibaba’s Earlier Move

January 5, 2024

Reuters reported this week that Baidu, China’s giant e-commerce and services provider, is exiting the quantum computing development arena. Reuters reported � Read more…

Leading Solution Providers

Contributors

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock 1179408610

Google Addresses the Mysteries of Its Hypercomputer 

December 28, 2023

When Google launched its Hypercomputer earlier this month (December 2023), the first reaction was, "Say what?" It turns out that the Hypercomputer is Google's t Read more…

AMD MI3000A

How AMD May Get Across the CUDA Moat

October 5, 2023

When discussing GenAI, the term "GPU" almost always enters the conversation and the topic often moves toward performance and access. Interestingly, the word "GPU" is assumed to mean "Nvidia" products. (As an aside, the popular Nvidia hardware used in GenAI are not technically... Read more…

Shutterstock 1606064203

Meta’s Zuckerberg Puts Its AI Future in the Hands of 600,000 GPUs

January 25, 2024

In under two minutes, Meta's CEO, Mark Zuckerberg, laid out the company's AI plans, which included a plan to build an artificial intelligence system with the eq Read more…

Google Introduces ‘Hypercomputer’ to Its AI Infrastructure

December 11, 2023

Google ran out of monikers to describe its new AI system released on December 7. Supercomputer perhaps wasn't an apt description, so it settled on Hypercomputer Read more…

China Is All In on a RISC-V Future

January 8, 2024

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "E Read more…

Intel Won’t Have a Xeon Max Chip with New Emerald Rapids CPU

December 14, 2023

As expected, Intel officially announced its 5th generation Xeon server chips codenamed Emerald Rapids at an event in New York City, where the focus was really o Read more…

IBM Quantum Summit: Two New QPUs, Upgraded Qiskit, 10-year Roadmap and More

December 4, 2023

IBM kicks off its annual Quantum Summit today and will announce a broad range of advances including its much-anticipated 1121-qubit Condor QPU, a smaller 133-qu Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire