July 14, 2006
With all the talk of heterogeneous supercomputing over the last few years, one might get the impression that a revolution is on the horizon. Certainly, some in the industry have portrayed it as such. Non-scalar vector processors, coprocessor accelerators, MTA processors and FPGAs are available today and can offer tantalizing performance for targeted HPC workloads. The general idea behind heterogeneous processing is that a system containing different kinds of compute engines can be matched up with the type of code that runs most efficiently on them, increasing overall application performance.
From an evolutionary standpoint, heterogeneous processing makes sense. As systems become more complex, a greater amount of architectural specialization is required. This appears to be true for both man-made systems and biological systems. Compare the sophisticated structure of the human brain with the simple bundles of neurons that control many primitive invertebrates.
In the scheme of things, today's computers are still rather primitive themselves, but they already contain many heterogeneous elements. At the level of the chipset, specialized I/O and memory controller devices are commonly used to manage an increasing array of data sources and destinations. Computer memory has differentiated into distinct types, the most common ones being RAM, ROM and cache (3 levels). The CPU has remained as one of the last general-purpose components of the system. But as applications -- especially HPC applications -- become more complex and more demanding of computational performance, the pressure to tap other types of processing engines will increase.
FPGAs (Field Programmable Gate Arrays), in particular, have been getting a lot attention lately. They have gained a loyal following in the supercomputing community because they are reconfigurable, have wide applicability for HPC applications, and are commodity-based. And unlike coprocessors, vector processors and MTA processors, FPGAs are more general-purpose compute engines.
The growing interest of the HPC community in IBM's Cell chip is another example. Although the chip contains both a scalar (PowerPC) CPU and vector compute engines, it is not considered a true heterogenous processor itself. The scalar CPU is used to control the vector cores and manage the chip's memory hierarchy, rather than for computation. But theoretically the Cell could be used an additional compute resource within a conventional scalar-based system.
All of these non-scalar processors have one thing in common: compared to commodity CPUs, there is not much code support for them. So the software will have catch up. And that's not going to happen overnight.
Today, the HPC software community is focusing much of its energy on applying code parallelism to scalar processors. Homogeneous multi-core architectures are currently in the driver's seat in high performance computing, as it will soon be in almost all IT markets. This trend is likely to continue for some time. High-volume 64-bit processors that are supported by mature software ecosystems, such as the AMD Opteron and the Intel Xeon (and to a lesser extent, POWER/PowerPC and Itanium), are delivering economical supercomputing performance for the masses. The fact that other microprocessor architectures may be faster, cheaper or more energy-efficient than industry-standard hardware doesn't have much impact on the market until someone figures out a way to mainstream the newer technology.
That usually means developing the appropriate software support for these exotic processors. And if the goal is to integrate that hardware into a truly heterogeneous system, a la Cray's "Adaptive Computing" vision, it will also involve the much more challenging problem of managing heterogeneity in system software. Our own High-End Crusader addressed this issue just a few weeks ago in the article title "Heterogeneous Processing Needs Software Revolutions."
To its credit, Cray is the only company that has offered a vision of integrated heterogeneous computing, both in hardware and software. But currently it's just a vision, not a product. Even the "Baker" petaflops system they plan to deliver to ORNL in 2008 is a homogeneous Opteron-based machine. Cray will implement their heterogeneous Cascade architecture when and if DARPA selects them for Phase 3 of the HPCS program. But the company says it intend to move forward with their Adaptive Computing roadmap whether they continue with HPCS or not. They believe that the next generation of high performance applications will require a variety of specialized compute engines to obtain reasonable performance (and use reasonable amounts of energy). Cray appears to be committed to that vision.
Other HPC vendors are venturing into the heterogenous space as well. SGI's Reconfigurable Application Specific Computing (RASC) technology represents their advanced FPGA solution. Sun Microsystem's recently deployed TSUBAME supercomputer incorporates ClearSpeed coprocessors (not in use yet, however) as part of that system. Other OEMs may come out with their own solutions in the next few years as software libraries and programmer development environments that support these new processor types become available.
But a heterogeneous architecture "revolution" seems unlikely while homogeneous multi-core architectures are so dominant in the commercial space. Revolutions usually start because the masses are unhappy, and that is not the case today. An "evolution" is far more likely and it is currently in progress. The mainstreaming of heterogeneous systems will happen sooner or later because parallelism, itself, has its limits. Bandwidth, memory access, and software scalability are already inhibiting performance on even moderately scaled systems (thousands of processors). Once we start building petaflops machines, these limitations will become even more aggravating. Heterogenous computing offers a way forward. Join the evolution!
As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at email@example.com.
Posted by Michael Feldman - July 13, 2006 @ 9:00 PM, Pacific Daylight Time
Michael Feldman is the editor of HPCwire.
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