April 28, 2006
This week, HPCwire spotlights the two companies that have driven the development of the Itanium microprocessor architecture, Intel and HP. In the second part of our conversation with Intel CTO, Justin Rattner, he talked about Intel's strategy for the microprocessor and his expectations for its future. From the HP perspective, Jerry Huck and Ed Turkel shared their thoughts about Itanium in the context of HP's Integrity systems. In this article, I'm going to offer some broader perspectives on the microprocessor's interesting history.
The Itanium has endured a controversial existence that has polarized not just the industry watchers, but the industry itself. First introduced in 2001, the microprocessor was advertised as the next generation 64-bit microprocessor, destined to replace the RISC architectures of the day. Some also claimed it would replace the CISC x86 microprocessors, as 32-bit platforms were phased out.
Here we are five years after its debut, awash in x86 machines, and Itanium is just beginning to establish itself in the higher end of the cluster and server market. While its proponents like to remind us that it has killed MIPS, Alpha and PA-RISC, the first two were more like assisted suicides and the latter is being forced into retirement by HP itself. So what happened?
At one time, Itanium was being considered by all the tier one OEMs. In 2000, Sun Microsystems decided to stick with their own Sparc-based systems and killed the Solaris-on-Itanium port. Last year, IBM dropped its plans for Itanium, concluding that the architecture would compete directly with its own beloved Power-based platforms. At the same time, it became apparent to Dell that the Itanium was too high-end for its product line. However, other OEMs such as SGI, Bull, Hitachi, Fujitsu and Unisys have stuck with Itanium.
In my conversations with the Rattner, Huck and Turkel, at least one thing became clear. The uninspiring introduction of Itanium with the performance-challenged Merced release in 2001, produced a bad first impression. Already late, the first product was pushed out the door before it was ready.
According to Intel's Justin Rattner, "it missed its original introduction target by several years. The implementation that came to market basically lost a two-year Moore's Law cycle and didn't have the overwhelming performance lead that it would have had it if it had come to market in say, 1998 as opposed to 2000. By the virtue of the fact that it was late, the implementation wasn't this kind of 'home run' from a performance point of view."
Jerry Huck at HP reflects those sentiments. "There probably was an over-stated expectation. People were expecting it to overtake the world in two years and it didn't, especially in the higher end of the market, which moves more slowly. It's just like the standard curve in technology adoption. We were too much in the hype side of the curve for awhile."
When the sequel, Itanium 2, arrived in 2002 with the McKinley chip, no one seemed to get too excited. Although the performance was much better -- and better yet in later implementations in 2003 and 2004 -- it wasn't exactly at the level that matched the original expectations. Itanium's EPIC (Explicitly Parallel Instruction Computing) architecture was advertised as a superior approach to both CISC and RISC. People were expecting something akin to a disruptive technology and they weren't getting it.
Part of this is a matter of perception. The pace of innovation has gotten everyone used to the immediate gratification that comes with rapid technology advancements. But there's a certain amount of conservatism built into technology adoption. This conservatism is even more pronounced in the high performance domain, where organizations with million dollar systems don't replace them every year just to double their performance. Most high-end commercial and government customers are on a three- to five-year cycle. And during economic downturns, like the one that coincided with Itanium's introduction, these procurement cycles get stretched.
Another development that blunted the early acceptance of the Itanium was the introduction AMD's 64-bit x86 processors. Now users who were looking for x86 compatibility with a 64-bit upgrade path could go for Opterons or Athlons. Itaniums had x86 compatibility support as well, but it was slow compared to a native implementation, and couldn't compete on price anyway. At this point, many industry watchers wondered if the microprocessor could find its niche. Three years later, its future is still in doubt.
Robin Bloor, in a recent article for IT-Director asks: "Will Itanium ever really make it? It's still too early to say, but it's very late to be too early to say."
Maybe. At five years old, Itanium is still an adolescent in the world of microprocessors.
Intel and HP appear to have come to terms with this reality and are practicing patience -- as you must with all adolescents. Ed Turkel, HP marketing manager for its HPC division, admits that Itanium is a relatively new technology and they're still learning how to best use it.
In the past year or so, Intel, HP and other Itanium proponents have regrouped. In 2005, the establishment of a well-funded Itanium Solution Alliance has accelerated the effort to get more software ported to the architecture -- 7000 applications and counting. Alliance members recently anteed up an additional $10 billion to help grow ecosystem support. In addition, the target market has been more narrowly focused to mission-critical server applications and HPC. Certainly, Itanium's superior floating point performance and it ability to address terabytes of memory point it towards high-end applications. Just recently the decision was made to jettison the processor's x86 compatibility circuitry, making room for more important features.
Despite the doubts about Itanium that you read about in the media, Intel and HP seem to be confident that the basic technology of the architecture will enable it to prevail in the marketplace. Says Jerry Huck at HP: "At the fundamental level, Itanium is really driving towards higher levels of instruction level parallelism. It's trying to achieve more work per cycle than what you accomplish in a RISC architecture. It does it with less hardware -- less built-in circuits for the purpose of trying to create parallelism."
In an article written last November by Johan De Gelas for AnandTech, he says: "From a purely technical and academic point of view -- completely ignoring the economical and business logic -- there are some strong indications that time may well be on the side of the EPIC CPU despite all doom scenarios."
The thrust of Gelas' argument is that Itanium's advantages in instruction level parallelism (ILP) and relatively small cores will give it a clear performance lead over its RISC and CISC rivals as semiconductor technology advances. As process technologies get smaller, proportionately more cores can added to the chip, giving it an advantage in Thread Level Parallelism (TLP). The smaller process will also make room for more on-chip cache which favors the cache-hungry Itanium more than its competitors.
So is this the year Itanium will enter adulthood? The soon-to-be-released dual-core Montecito might be the breakthrough chip for the architecture. By going to two cores, Intel has managed to double the performance within the same thermal envelope. And after 2006, the road map shows increases in both core count and clock speed. Confidence by Intel, HP and other Itanium server OEMs abounds.
Declares Rattner: "We firmly believe that it is destined to become the high-volume post-RISC microprocessor out there."
-- Michael Feldman
Posted by Michael Feldman - April 27, 2006 @ 9:00 PM, Pacific Daylight Time
Michael Feldman is the editor of HPCwire.
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