December 16, 2005
Xilinx, Inc. has announced the 8.1i release of its Integrated Software Environment (ISE) design tool suite, which features the new ISE Fmax technology with enhanced physical synthesis capabilities to improve performance and timing closure for both the Virtex-4 and Spartan-3 architectures. Using ISE 8.1i software, designers can boost performance by an average of 10 to 37 percent as compared to previous ISE releases and up to 70 percent over competing solutions using Virtex-4 FPGAs. ISE 8.1i also delivers enhancements to its partial reconfiguration technology, enabling lower cost, size and power consumption.
Offering an average of a speed grade in cost savings from the previous ISE version, the new features are aimed at strengthening Xilinx solutions for high-performance system design, including designs that feature embedded processing, digital signal processing (DSP) and advanced connectivity protocols. According to Xilinx, because of the use of advanced physical synthesis capabilities in the ISE tools, designers can maximize performance throughput, accelerate time to market, and reduce overall development costs. In addition, features such as ChipScope Pro 8.1i in-silicon debug integration and more robust partial reconfiguration support further drive down development time and system costs.
"We are constantly working with designers to solve their key challenges -- timing closure, cost and systems-design complexity. ISE 8.1i addresses these with advanced design compilation optimizations, delivering substantial automated Fmax improvements and offering intuitive new interface features," said Bruce Talley, vice president of the Design Software Division at Xilinx. "Designers now have more certainty of meeting system performance, functionality and cost targets for their end products."
The new ISE Fmax technology employs new algorithms to improve the results of physical synthesis and logic optimization resulting in up to a 70 percent performance advantage for Virtex-4 FPGAs over competing devices. ISE Fmax Technology includes a full set of features for design retiming, timing-driven packing and placement, performance evaluation and post-placement logic optimization. The ISE Xplorer utility, included with the latest release, is a script that helps designers evaluate and optimize the Virtex-4 and Spartan-3 FPGA performance, delivering an average of 10 percent improvement over previous releases for timing driven designs. ISE 8.1i offers a performance evaluation mode that delivers a 37 percent out-of-the box performance improvement for designs without timing constraints.
ISE Fmax technology is complementary to synthesis optimizations from Synplicity and Mentor Graphics. The combination of synthesis and ISE Fmax technologies enables users to meet stringent timing goals.
"The new ISE 8.1i software in combination with the Synplify Pro synthesis products give Xilinx FPGA designers an advantage when pushing timing performance," said Jeff Garrison, director of marketing for FPGA Products at Synplicity, Inc. "We continue to work closely with Xilinx to ensure that our newest technologies, such as our Graph-based physical synthesis recently introduced in our Synplify Premier product, interface with ISE software to deliver the fastest timing closure for the entire line of Xilinx FPGAs."
"The tight integration of Mentor Graphics advanced Precision Synthesis solution into the Xilinx ISE 8.1i release opens up the best features of both environments for our mutual customers," said Simon Bloch, general manager, Design Creation and Synthesis Division, Mentor Graphics. "The customer-proven design analysis technology in Precision Synthesis, which delivers the right balance of automated/interactive optimizations and user control, now complements the industry-leading Xilinx Fmax Technology available in ISE 8.1i."
With the 8.1i release, Xilinx has added a new methodology to enhance its partial reconfiguration solution. Partial reconfiguration reduces system cost, size, device count, and power consumption, useful for a wide variety of applications, such as Software Defined Radio (SDR) and high performance computing. Designers can now dynamically load different hardware configurations into the same area of the FPGA while the rest of the device continues running. This real-time dimension to programmability builds upon field upgradeability and multi-boot approaches that have enabled many Xilinx customers to boost system reliability with real-time diagnostics, lower field service costs and extend the lifespan of existing products in the marketplace.
ISE 8.1i offers 37 percent faster push button in the performance evaluation mode, enabling evaluation of designs without need for constraints. ISE 8.1i also offers support for dual-core CPU workstations, enabling faster compile times and parallel processing of design jobs across multiple CPU cores. These capabilities are further bolstered by XPower, a power analysis solution, improved web analysis capabilities in WebPower Tools 8.1i, and new power optimized routing technology. ISE 8.1i Project Navigator and integrated ISE Simulator tool offer a new intuitive Windows XPTM look and feel on all platforms.
The release of ChipScope Pro 8.1i provides an integrated debug solution -- up to 50x times faster than simulation. The ChipScope Pro core resource estimator enables users to explore on-chip debug and verification options such as trigger width, sample depth, and advanced capabilities such as trigger sequencing and storage qualification to determine the optimal trade off between on-chip visibility and FPGA resource allocation.
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