|The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing / July 20, 2007|
July 18 -- High-performance reconfigurable computing (HPRC) based on the combination of conventional microprocessors and field-programmable gate arrays (FPGA) offers the potential to dramatically accelerate computationally intensive scientific applications. In conjunction with SC07, there will be a workshop on High-Performance Reconfigurable Computing Technology and Applications (Reno, Nevada, Nov. 11, 2007). The goal of this workshop is to provide a forum for academic researchers and industry representatives to discuss the latest trends and developments in the field, and to set a research agenda for the upcoming years.
Submissions are solicited on a wide variety of topics related to HPRC, including but not limited to:
Full-length papers up 10 pages are solicited. Submissions are due Sept. 15, 2007; authors will be notified of paper acceptable by Oct. 15, and final camera-ready manuscripts will be due Nov. 1. Authors should submit PDF documents to email@example.com.
All papers selected for this workshop will be peer-reviewed. The authors of accepted papers will be scheduled to present their work in one of the technical sessions. Workshop proceedings will be included in the ACM Digital Library and the best papers presented at the workshop will be considered for inclusion in a special issue of the ACM Transactions on Reconfigurable Technology and Systems (TRETS). Detailed paper submission instructions will be provided online at http://www.ncsa.uiuc.edu/Conferences/HPRCTA07/.
The workshop on High-Performance Reconfigurable Computing Technology and Applications is sponsored by the National Center for Supercomputing Applications, George Washington University, University of South Carolina, and George Mason University.
Source: National Center for Supercomputing Applications